Jennifer Hasler

Affiliations:	1992-1997	Computation and Neural Systems	California Institute of Technology, Pasadena, CA
	1997-	Electrical and Computer Engineering	Georgia Institute of Technology, Atlanta, GA

Area:

Biomedical Engineering, Electronics and Electrical Engineering, Artificial Intelligence

Website:

http://hasler.ece.gatech.edu

Google:

"Jennifer Hasler"

Bio:

aka Paul Hasler
Hasler, Paul Edward (1997) Foundations of learning in analog VLSI. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/2J7M-GE02.

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Parents

Carver Mead	grad student	1992-1997	Caltech (Neurotree)
(Foundations of learning in analog VLSI)

Children

Jeff Dugger	grad student	2003	Georgia Tech (MathTree)
Abhishek Bandyopadhyay	grad student	2004	Georgia Tech (MathTree)
Matthew R. Kucic	grad student	2004	Georgia Tech (MathTree)
Ravi Chawla	grad student	2005	Georgia Tech (MathTree)
Ethan D. Farquhar	grad student	2005	Georgia Tech (MathTree)
Mark S. Hooper	grad student	2005	Georgia Tech (MathTree)
Erhan Ozalevli	grad student	2006	Georgia Tech (MathTree)
Gail L. Rosen	grad student	2006	Georgia Tech (MathTree)
Venkatesh Srinivasan	grad student	2006	Georgia Tech (MathTree)
Christopher M. Twigg	grad student	2006	Georgia Tech (MathTree)
Guillermo J. Serrano	grad student	2007	Georgia Tech (MathTree)
David Abramson	grad student	2008	Georgia Tech (MathTree)
Kofi Odame	grad student	2008	Georgia Tech (MathTree)
Sheng-Yu Peng	grad student	2008	Georgia Tech (MathTree)
Christal Gordon	grad student	2009	Georgia Tech (MathTree)
Jordan D. Gray	grad student	2009	Georgia Tech (MathTree)
Bo Marr	grad student	2009	Georgia Tech (MathTree)
Muhammad S. Qureshi	grad student	2009	Georgia Tech (MathTree)
Ryan W. Robucci	grad student	2009	Georgia Tech (MathTree)
Jason George	grad student	2011	Georgia Tech (MathTree)
Gokce Gurun	grad student	2011	Georgia Tech (MathTree)
Sangwook Suh	grad student	2011	Georgia Tech (MathTree)
Stephen Brink	grad student	2012	Georgia Tech
Craig R. Schlottman	grad student	2012	Georgia Tech

Collaborators

BETA: Related publications

Publications

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Shah S, Toreyin H, Gungor CB, et al. (2019) A Real-Time Vital-Sign Monitoring in the Physical Domain on a Mixed-Signal Reconfigurable Platform. Ieee Transactions On Biomedical Circuits and Systems
Hasler J. (2019) Analog Architecture Complexity Theory Empowering Ultra-Low Power Configurable Analog and Mixed Mode SoC Systems Journal of Low Power Electronics and Applications. 9: 4
Thakur CS, Molin JL, Cauwenberghs G, et al. (2018) Corrigendum: Large-Scale Neuromorphic Spiking Array Processors: A Quest to Mimic the Brain. Frontiers in Neuroscience. 12: 991
Natarajan A, Hasler J. (2018) Hodgkin-Huxley Neuron and FPAA Dynamics. Ieee Transactions On Biomedical Circuits and Systems
Hasler J, Natarajan A, Kim S. (2018) Enabling Energy-Efficient Physical Computing through Analog Abstraction and IP Reuse Journal of Low Power Electronics and Applications. 8: 47
Hasler J, Shah S. (2018) Security Implications for Ultra-Low Power Configurable SoC FPAA Embedded Systems Journal of Low Power Electronics and Applications. 8: 17
Shah S, Toreyin H, Hasler J, et al. (2018) Temperature Sensitivity and Compensation on a Reconfigurable Platform Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 26: 604-607
Shah S, Hasler J. (2018) SoC FPAA Hardware Implementation of a VMM+WTA Embedded Learning Classifier Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 8: 28-37
Hasler J, Shah S. (2018) VMM + WTA Embedded Classifiers Learning Algorithm Implementable on SoC FPAA Devices Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 8: 65-76
Shah S, Toreyin H, Hasler J, et al. (2017) Models and Techniques for Temperature Robust Systems on a Reconfigurable Platform Journal of Low Power Electronics and Applications. 7: 21