Dimitri P. Ioannou, Ph.D.
Affiliations: | 2007 | George Mason University, Washington, DC |
Area:
Electronics and Electrical EngineeringGoogle:
"Dimitri Ioannou"Mean distance: (not calculated yet)
Parents
Sign in to add mentor| Mulpuri V. Rao | grad student | 2007 | George Mason | |
| (Reliability and performance issues in nanoscale SOI CMOS.) | ||||
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Publications
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| Ioannou DP. (2014) HKMG CMOS technology qualification: The PBTI reliability challenge Microelectronics Reliability. 54: 1489-1499 |
| Ioannou DP, Mittl S, Brochu D. (2012) Burn-in stress induced BTI degradation and post-burn-in high temperature anneal (bake) effects in advanced HKMG and oxynitride based CMOS ring oscillators Ieee International Reliability Physics Symposium Proceedings |
| Ioannou DP, Zhao K, Bansal A, et al. (2011) A robust reliability methodology for accurately predicting Bias Temperature Instability induced circuit performance degradation in HKMG CMOS Ieee International Reliability Physics Symposium Proceedings |
| Ioannou DP, Harmon D, Abadeer W. (2009) Investigation of plasma charging damage impact on device and gate dielectric reliability in 180nm SOI CMOS RF switch technology Ieee International Reliability Physics Symposium Proceedings. 1011-1013 |
| Ioannou DP, Ioannou DE. (2007) Some issues of hot-carrier degradation and negative bias temperature instability of advanced SOI CMOS transistors Solid-State Electronics. 51: 268-277 |
| Ioannou DP, Ioannou DE. (2004) Beta engineering and circuit styles for SEU hardening PD-SOI SRAM cells Solid-State Electronics. 48: 1947-1951 |
| Mitra S, Salman A, Ioannou DP, et al. (2003) DG-SO1 ratioed logic with symmetric DG load -a novel approach for sub 50 nm LV/LP circuit design 2003 International Semiconductor Device Research Symposium, Isdrs 2003 - Proceedings. 390-391 |
| Mitra S, Salman A, Ioannou DP, et al. (2003) Low Voltage / Low Power sub 50 nm Double Gate SOI Ratioed Logic Ieee International Soi Conference. 177-178 |
| Mitra S, Salman A, Ioannou DP, et al. (2002) LP/LV ratioed DG-SOI logic with (intrinsically on) symmetric DG-MOSFET load Ieee International Soi Conference. 66-67 |