Krishna M. Kavi

Affiliations: 
1980-1982 University of Louisiana at Lafayette, Lafayette, LA, United States 
 1982-1997 Computer Science and Engineering University of Texas at Arlington, Arlington, TX, United States 
 1997-2001 Electrical and Computer Engineering The University of Alabama in Huntsville, Huntsville, AL, United States 
 2001-2009 Computer Science and Engineering University of North Texas, Denton, TX, United States 
Area:
Computer Science
Website:
https://computerscience.engineering.unt.edu/people/faculty/krishna-kavi
Google:
"Krishna Murthy Kavipurapu" OR "Krishna M. Kavi"
Bio:

https://csrl.cse.unt.edu/kavi/
https://ieeexplore.ieee.org/author/37295249100
https://books.google.com/books?id=_7uNnQEACAAJ
https://books.google.com/books?id=zZwvAQAAIAAJ

Parents

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Harvey G. Cragon grad student 1980 SMU
 (The Design of Architectures to Reduce Semantic Gap)
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Publications

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Islam M, Adavally S, Scrbak M, et al. (2020) On-the-fly Page Migration and Address Reconciliation for Heterogeneous Memory Systems Acm Journal On Emerging Technologies in Computing Systems. 16: 1-27
Shelor C, Kavi K. (2017) Dataflow based Near Data Computing Achieves Excellent Energy Efficiency Heart. 6
Shidal J, Spilo AJ, Scheid PT, et al. (2015) Recycling trash in cache International Symposium On Memory Management, Ismm. 14: 118-130
Kavi K, Pianelli S, Pisano G, et al. (2015) Memory organizations for 3D-DRAMs and PCMs in processor memory hierarchy Journal of Systems Architecture. 61: 539-552
Shelor CF, Kavi KM. (2015) Moola: Multicore cache simulator Proceedings of the 30th International Conference On Computers and Their Applications, Cata 2015. 357-362
Janjusic T, Kavi K. (2014) Hardware and application profiling tools Advances in Computers. 92: 105-160
Kavi K, Pianelli S, Pisano G, et al. (2014) 3D DRAM and PCMs in processor memory hierarchy Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 8350: 183-195
Shelor C, Buchanan J, Kavi K, et al. (2014) Quantifying wasted write energy in the memory hierarchy 29th International Conference On Computers and Their Applications, Cata 2014. 127-134
Shelor C, Buchanan J, Kavi K, et al. (2014) Potential energy savings through eliminating unnecessary rites in the cache-memory hierarchy International Journal of Computers and Their Applications. 21: 178-187
Islam M, Scrbak M, Kavi KM, et al. (2014) Improving node-level mapreduce performance using processing-in-memory technologies Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 8806: 425-437
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