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Sudhakar Yalamanchili

Affiliations: 
Georgia Institute of Technology, Atlanta, GA 
Area:
Electronics and Electrical Engineering, Computer Science
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"Sudhakar Yalamanchili"
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Craig D. Ulmer grad student 2002 Georgia Tech
Rajaram B. Krishnamurthy grad student 2003 Georgia Tech
Subramanian Ramaswamy grad student 2008 Georgia Tech
Gregory F. Diamos grad student 2011 Georgia Tech

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Publications

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Asgari B, Mukhopadhyay S, Yalamanchili S. (2020) MAHASIM: Machine-Learning Hardware Acceleration Using a Software-Defined Intelligent Memory System Journal of Signal Processing Systems. 1-17
Mukhopadhyay S, Long Y, Mudassar BA, et al. (2019) Heterogeneous integration for artificial intelligence: Challenges and opportunities Journal of Reproduction and Development. 63
Asgari B, Hadidi R, Kim H, et al. (2019) ERIDANUS: Efficiently Running Inference of DNNs Using Systolic Arrays Ieee Micro. 39: 46-54
Kim D, Na T, Yalamanchili S, et al. (2018) DeepTrain: A Programmable Embedded Platform for Training Deep Neural Networks Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 2360-2370
Chen X, Xiao H, Wardi Y, et al. (2018) On-line Optimization of Power Efficiency in 3D Multicore Processors Ifac-Papersonline. 51: 127-132
Chen X, Wardi Y, Yalamanchili S. (2018) Instruction-throughput regulation in computer processors with data-center applications Discrete Event Dynamic Systems. 28: 127-158
Yueh W, Wan Z, Xiao H, et al. (2017) Active Fluidic Cooling on Energy Constrained System-on-Chip Systems Ieee Transactions On Components, Packaging and Manufacturing Technology. 7: 1813-1822
Wang J, Dong Z, Yalamanchili S, et al. (2016) FNM: An enhanced null-message algorithm for parallel simulation of multicore systems Acm Transactions On Modeling and Computer Simulation. 26
Chen X, Wardi Y, Yalamanchili S. (2016) IPA in the loop: Control design for throughput regulation in computer processors 2016 13th International Workshop On Discrete Event Systems, Wodes 2016. 141-146
Xiao H, Yueh W, Mukhopadhyay S, et al. (2016) Thermally Adaptive Cache Access Mechanisms for 3D Many-Core Architectures Ieee Computer Architecture Letters. 15: 129-132
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