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Vijaykrishnan Narayanan

Affiliations: 
Pennsylvania State University, State College, PA, United States 
Area:
Computer Science
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Parents

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Nagarajan Ranganathan grad student 1993-1998 University of South Florida

Children

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Jie Hu grad student
Soontae Kim grad student 2003 Penn State
Yuh-Fang Tsai grad student 2005 Penn State
Theocharis Theocharides grad student 2002-2005 Penn State
Aman Gayasen grad student 2006 Penn State
Jooheung Lee grad student 2006 Penn State
Gregory M. Link grad student 2006 Penn State
Chrysostomos Nicopoulos grad student 2007 Penn State
Ing-Chao Lin grad student 2002-2007 Penn State
Ramakrishnan Krishnan grad student 2010 Penn State
Prasanth Mangalagiri grad student 2010 Penn State
Andrew J. Ricketts grad student 2010 Penn State
Vinay Saripalli grad student 2011 Penn State
Srinidhi Kestur Vyasa Prasanna grad student 2012 Penn State
Karthik Swaminathan grad student 2014 Penn State

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Publications

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Zhong H, Gu M, Wang Y, et al. (2020) One-Shot Refresh: A Low-Power Low-Congestion Approach for Dynamic Memories Ieee Transactions On Circuits and Systems Ii-Express Briefs. 1-1
Anderson S, Challapalle N, Sampson J, et al. (2020) Adaptive Neural Network Architectures for Power Aware Inference Ieee Design & Test of Computers. 37: 66-75
Liang Y, Zhu Z, Li X, et al. (2019) Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 27: 2855-2860
Rangachar Srinivasa S, Ramanathan AK, Li X, et al. (2019) ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support Ieee Transactions On Circuits and Systems I: Regular Papers. 66: 2533-2545
Li X, Wu J, Ni K, et al. (2019) Design of 2T/Cell and 3T/Cell Nonvolatile Memories with Emerging Ferroelectric FETs Ieee Design & Test of Computers. 36: 39-45
Yoon I, Khan A, Datta S, et al. (2019) A FerroFET-Based In-Memory Processor for Solving Distributed and Iterative Optimizations via Least-Squares Method Ieee Journal On Exploratory Solid-State Computational Devices and Circuits. 5: 132-141
George S, Li X, Liao MJ, et al. (2018) Symmetric 2-D-Memory Access to Multidimensional Data Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 26: 1040-1050
Srinivasa S, Li X, Chang M, et al. (2018) Compact 3-D-SRAM Memory With Concurrent Row and Column Data Access Capability Using Sequential Monolithic 3-D Integration Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 26: 671-683
Liang Y, Li X, Gupta SK, et al. (2018) Analysis of DIBL Effect and Negative Resistance Performance for NCFET Based on a Compact SPICE Model Ieee Transactions On Electron Devices. 65: 5525-5529
Liang Y, Li X, George S, et al. (2018) Influence of Body Effect on Sample-and-Hold Circuit Design Using Negative Capacitance FET Ieee Transactions On Electron Devices. 65: 3909-3914
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