Dan Nicolaescu, Ph.D.
Affiliations: | 2006 | University of California, Irvine, Irvine, CA |
Area:
Computer ScienceGoogle:
"Dan Nicolaescu"Parents
Sign in to add mentor| Alexander Veidenbaum | grad student | 2006 | UC Irvine | |
| (Cache power-performance optimization.) | ||||
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Publications
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| Nicolaescu D, Veidenbaum A, Nicolau A. (2008) Using a way cache to improve performance of set-associative caches Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 4759: 93-104 |
| Nicolaescu D, Salamat B, Veidenbaum A, et al. (2006) Fast speculative address generation and way caching for reducing L1 data cache energy Ieee International Conference On Computer Design, Iccd 2006. 101-107 |
| Nicolaescu D, Veidenbaum A. (2005) Understanding and comparing the performance of optimized JVMs Proceedings of the Innovative Architecture For Future Generation High-Performance Processors and Systems. 2005: 45-52 |
| Nicolaescu D, Veidenbaum A, Nicolau A. (2004) Caching values in the load store queue Proceedings - Ieee Computer Society's Annual International Symposium On Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, Mascots. 580-587 |
| Veidenbaum A, Nicolaescu D. (2004) Low energy, highly-associative cache design for embedded processors Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 332-335 |
| Aragon JL, Nicolaescu D, Veidenbaum A, et al. (2004) Energy-efficient design for highly associative instruction caches in next-generation embedded processors Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 2: 1374-1375 |
| Nicolaescu D, Veidenbaum A, Nicolau A. (2003) Reducing power consumption for high-associativity data caches in embedded processors Proceedings -Design, Automation and Test in Europe, Date. 1064-1068 |
| Nicolaescu D, Veidenbaum A, Nicolau A. (2003) Reducing Data Cache Energy Consumption via Cached Load/Store Queue Proceedings of the International Symposium On Low Power Electronics and Design. 252-257 |
| Nicolaescu D, Ji X, Veidenbaum A, et al. (2001) Compiler-directed cache line size adaptivity Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 2107: 183-187 |
| Ji X, Nicolaescu D, Veidenbaum A, et al. (2000) Compiler–directed cache assist adaptivity Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1940: 88-104 |