Vinay Saripalli, Ph.D.
Affiliations: | 2011 | Computer Science and Engineering | Pennsylvania State University, State College, PA, United States |
Area:
Computer Engineering, Electronics and Electrical Engineering, NanotechnologyGoogle:
"Vinay Saripalli"Parents
Sign in to add mentor| Vijaykrishnan Narayanan | grad student | 2011 | Penn State | |
| (Device and architecture co-design for ultra-low power logic using emerging tunneling-based devices.) | ||||
BETA: Related publications
See more...
Publications
|
You can help our author matching system! If you notice any publications incorrectly attributed to this author, please sign in and mark matches as correct or incorrect. |
| Pandey R, Saripalli V, Kulkarni JP, et al. (2014) Impact of single trap random telegraph noise on heterojunction TFET SRAM stability Ieee Electron Device Letters. 35: 393-395 |
| Swaminathan K, Kultursay E, Saripalli V, et al. (2013) Steep-slope devices: From dark to dim silicon Ieee Micro. 33: 50-59 |
| Mukundrajan R, Cotter M, Bae S, et al. (2013) Design of energy-efficient circuits and systems using tunnel field effect transistors Iet Circuits, Devices and Systems. 7: 294-303 |
| Kultursay E, Swaminathan K, Saripalli V, et al. (2012) Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores Codes+Isss'12 - Proceedings of the 10th Acm International Conference On Hardware/Software-Codesign and System Synthesis, Co-Located With Esweek. 245-254 |
| Swaminathan K, Kultursay E, Saripalli V, et al. (2012) Design space exploration of workload-specific last-level caches Proceedings of the International Symposium On Low Power Electronics and Design. 243-248 |
| Madan H, Saripalli V, Liu H, et al. (2012) Asymmetric tunnel field-effect transistors as frequency multipliers Ieee Electron Device Letters. 33: 1547-1549 |
| Mukundrajan R, Cotter M, Saripalli V, et al. (2012) Ultra low power circuit design using tunnel FETs Proceedings - 2012 Ieee Computer Society Annual Symposium On Vlsi, Isvlsi 2012. 153-158 |
| Liu H, Mohata DK, Nidhi A, et al. (2012) Exploration of vertical MOSFET and tunnel FET device architecture for Sub 10nm node applications Device Research Conference - Conference Digest, Drc. 233-234 |
| Saripalli V, Datta S, Narayanan V, et al. (2011) Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design Proceedings of the 2011 Ieee/Acm International Symposium On Nanoscale Architectures, Nanoarch 2011. 45-52 |
| Saripalli V, Sun G, Mishra A, et al. (2011) Exploiting heterogeneity for energy efficiency in chip multiprocessors Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 1: 109-119 |