Noureddine Chabini, Ph.D.
Affiliations: | 2001 | Université de Montréal, Montréal, Canada |
Area:
Computer Science, Electronics and Electrical EngineeringGoogle:
"Noureddine Chabini"Parents
Sign in to add mentor| El Mostapha Aboulhamid | grad student | 2001 | Université de Montréal | |
| (Methodes pour ameliorer la qualite des implantations materielles de systemes informatiques.) | ||||
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Publications
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| Najoui M, Hatim A, Belkouch S, et al. (2020) Novel Implementation Approach with Enhanced Memory Access Performance of MGS Algorithm for VLIW Architecture Journal of Circuits, Systems, and Computers. 2050200 |
| Gao S, Al-Khalili D, Langlois JMP, et al. (2017) Efficient Realization of BCD Multipliers Using FPGAs International Journal of Reconfigurable Computing. 2017: 1-12 |
| Najoui M, Bahtat M, Hatim A, et al. (2017) VLIW DSP-Based Low-Level Instruction Scheme of Givens QR Decomposition for Real-Time Processing Journal of Circuits, Systems, and Computers. 26: 1750129 |
| Gao S, Al-Khalili D, Chabini N. (2016) Optimized large size signed multipliers and applications in FPGAs Proceedings - 2010 1st Ieee Latin American Symposium On Circuits and Systems, Lascas 2010. 73-76 |
| Chabini N, Belkouch S. (2016) Area and delay aware approaches for realizing multi-operand addition on FPGAs using two-operand adders Proceedings of Ieee/Acs International Conference On Computer Systems and Applications, Aiccsa. 2016 |
| Hatim A, Belkouch S, El Aakif M, et al. (2013) Design optimization of the quantization and a pipelined 2D-DCT for real-time applications Multimedia Tools and Applications. 67: 667-685 |
| Gao S, Al-Khalili D, Chabini N. (2012) An improved BCD adder using 6-LUT FPGAs 2012 Ieee 10th International New Circuits and Systems Conference, Newcas 2012. 13-16 |
| Gao S, Al-Khalili D, Chabini N, et al. (2012) Asymmetric large size multipliers with optimised FPGA resource utilisation Iet Computers and Digital Techniques. 6: 372-383 |
| Gao S, Al-Khalili D, Chabini N. (2012) FPGA realization of high performance large size computational functions: Multipliers and applications Analog Integrated Circuits and Signal Processing. 70: 165-179 |
| Anas H, Belkouch S, El Aakif M, et al. (2011) FPGA implementation of a pipelined 2D-DCT and simplified quantization for real-time applications International Conference On Multimedia Computing and Systems -Proceedings |