Daniel Sorin
Affiliations: | Computer Science | Duke University, Durham, NC |
Area:
Computer ScienceGoogle:
"Daniel Sorin"Children
Sign in to add trainee| Albert Meixner | grad student | 2008 | Duke |
| Anita Lungu | grad student | 2009 | Duke |
| Fred A. Bower | grad student | 2010 | Duke |
| Bogdan F. Romanescu | grad student | 2010 | Duke |
| Blake Hechtman | grad student | 2014 | Duke |
| Adam Jacobvitz | grad student | 2014 | Duke |
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Publications
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| Martin M, Sorin D. (2016) Top Picks from the 2015 Computer Architecture Conferences Ieee Micro. 36: 6-9 |
| Jacobvitz AN, Hilton AD, Sorin DJ. (2015) Multi-program benchmark definition Ispass 2015 - Ieee International Symposium On Performance Analysis of Systems and Software. 72-82 |
| Hechtman BA, Sorin DJ. (2013) Exploring memory consistency for massively-threaded throughput-oriented processors Proceedings - International Symposium On Computer Architecture. 201-212 |
| Hechtman BA, Sorin DJ. (2013) Evaluating cache coherent shared virtual memory for heterogeneous multicore chips Ispass 2013 - Ieee International Symposium On Performance Analysis of Systems and Software. 118-119 |
| Jacobvitz AN, Calderbank R, Sorin DJ. (2013) Coset coding to extend the lifetime of memory Proceedings - International Symposium On High-Performance Computer Architecture. 222-233 |
| Jacobvitz AN, Calderbank R, Sorin DJ. (2012) Writing cosets of a convolutional code to increase the Lifetime of Flash memory 2012 50th Annual Allerton Conference On Communication, Control, and Computing, Allerton 2012. 308-318 |
| Sorin DJ, Hill MD, Wood DA. (2011) A primer on memory consistency and cache coherence Synthesis Lectures On Computer Architecture. 16: 1-212 |
| Eibl PJ, Meixner A, Sorin DJ. (2011) An FPGA-based experimental evaluation of microprocessor core error detection with Argus-2 Performance Evaluation Review. 39: 121-122 |
| Romanescu B, Lebeck A, Sorin DJ. (2011) Address translation aware memory consistency Ieee Micro. 31: 109-118 |
| Gizopoulos D, Psarakis M, Adve SV, et al. (2011) Architectures for online error detection and recovery in multicore processors Proceedings -Design, Automation and Test in Europe, Date. 533-538 |