Himanshu Kaul, Ph.D.
Affiliations: | 2005 | University of Michigan, Ann Arbor, Ann Arbor, MI |
Area:
Electronics and Electrical EngineeringGoogle:
"Himanshu Kaul"Parents
Sign in to add mentor| Dennis M. Sylvester | grad student | 2005 | University of Michigan | |
| (On -chip signaling techniques for nanometer VLSI designs.) | ||||
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Publications
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| Kumar R, Suresh V, Kar M, et al. (2020) A 4900-$\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition Ieee Journal of Solid-State Circuits. 55: 945-955 |
| Satpathy SK, Mathew SK, Kumar R, et al. (2019) An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS Ieee Journal of Solid-State Circuits. 54: 1074-1085 |
| Satpathy S, Mathew SK, Suresh V, et al. (2017) A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS Ieee Journal of Solid-State Circuits. 52: 940-949 |
| Mathew SK, Johnston D, Satpathy S, et al. (2016) μrNG: A 300-950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS Ieee Journal of Solid-State Circuits. 51: 1695-1704 |
| Kaul H, Anders MA, Mathew SK, et al. (2016) 14.4 A 21.5M-query-vectors/s 3.37nJ/vector reconfigurable k-nearest-neighbor accelerator with adaptive precision in 14nm tri-gate CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 59: 260-261 |
| Mathew S, Satpathy S, Suresh V, et al. (2015) 340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(24)2 Polynomials in 22 nm Tri-Gate CMOS Ieee Journal of Solid-State Circuits. 50: 1048-1058 |
| Mathew SK, Satpathy SK, Anders MA, et al. (2014) 16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 57: 278-279 |
| Hsu SK, Agarwal A, Anders MA, et al. (2013) A 280 mV-to-1.1 v 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22 nm tri-gate CMOS Ieee Journal of Solid-State Circuits. 48: 118-127 |
| Mathew SK, Srinivasan S, Anders MA, et al. (2012) 2.4 Gbps, 7 mW all-digital PVT-variation tolerant true random number generator for 45 nm CMOS high-performance microprocessors Ieee Journal of Solid-State Circuits. 47: 2807-2821 |
| Kaul H, Anders M, Mathew S, et al. (2012) A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 55: 182-183 |