Marcin Rogawski, Ph.D.
Affiliations: | 2013 | Electrical and Computer Engineering | George Mason University, Washington, DC |
Area:
Computer EngineeringGoogle:
"Marcin Rogawski"Parents
Sign in to add mentor| Kris Gaj | grad student | 2013 | George Mason | |
| (Development and Benchmarking of New Hardware Architectures for Emerging Cryptographic Transformations.) | ||||
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Publications
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| Rogawski M, Homsirikamol E, Gaj K. (2014) A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs Conference Digest - 24th International Conference On Field Programmable Logic and Applications, Fpl 2014 |
| Rogawski M, Gaj K, Homsirikamol E. (2013) A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grøstl Microprocessors and Microsystems. 37: 572-582 |
| Rogawski M, Gaj K. (2012) A high-speed unified hardware architecture for AES and the SHA-3 candidate Grøstl Proceedings - 15th Euromicro Conference On Digital System Design, Dsd 2012. 568-575 |
| Salman A, Rogawski M, Kaps JP. (2011) Efficient hardware accelerator for IPSec based on partial reconfiguration on Xilinx FPGAs Proceedings - 2011 International Conference On Reconfigurable Computing and Fpgas, Reconfig 2011. 242-248 |
| Shahid R, Sharif MU, Rogawski M, et al. (2011) Use of embedded FPGA resources in implementations of 14 round 2 SHA-3 candidates 2011 International Conference On Field-Programmable Technology, Fpt 2011 |
| Homsirikamol E, Rogawski M, Gaj K. (2011) Throughput vs. area trade-offs in high-speed architectures of five round 3 SHA-3 candidates implemented using xilinx and altera FPGAs Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 6917: 491-506 |
| Gaj K, Kwon S, Baier P, et al. (2010) Area-time efficient implementation of the elliptic curve method of factoring in reconfigurable hardware for application in the number field sieve Ieee Transactions On Computers. 59: 1264-1280 |
| Gaj K, Homsirikamol E, Rogawski M. (2010) Fair and comprehensive methodology for comparing hardware performance of fourteen round two SHA-3 candidates using FPGAs Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 6225: 264-278 |