Smruti R. Sarangi, Ph.D.
Affiliations: | 2007 | University of Illinois, Urbana-Champaign, Urbana-Champaign, IL |
Area:
Computer ScienceGoogle:
"Smruti Sarangi"Parents
Sign in to add mentor| Josep Torrellas | grad student | 2007 | UIUC | |
| (Techniques to mitigate the effects of congenital faults in processors.) | ||||
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Publications
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| Jindal N, Gupta S, Ravipati DP, et al. (2020) Enhancing Network-on-Chip Performance by Reusing Trace Buffers Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 922-935 |
| Moolchandani D, Kumar A, Sarangi SR. (2020) Accelerating CNN Inference on ASICs: A survey Journal of Systems Architecture. 101887 |
| Sultan H, Chauhan A, Sarangi SR. (2019) A Survey of Chip-level Thermal Simulators Acm Computing Surveys. 52: 42 |
| Bashir J, Peter E, Sarangi SR. (2019) BigBus: A Scalable Optical Interconnect Acm Journal On Emerging Technologies in Computing Systems. 15: 1-24 |
| Ananthanarayanan G, Sarangi SR, Balakrishnan M. (2018) Task Assignment Algorithms for Multicore Platforms with Process Variations Journal of Low Power Electronics. 14: 302-317 |
| Kalayappan R, Sarangi SR. (2018) Providing Accountability in Heterogeneous Systems-on-Chip Acm Transactions in Embedded Computing Systems. 17: 83 |
| Jindal N, Panda PR, Sarangi SR. (2018) Reusing Trace Buffers as Victim Caches Ieee Transactions On Very Large Scale Integration Systems. 26: 1699-1712 |
| Chandran S, Panda PR, Sarangi SR, et al. (2017) Managing Trace Summaries to Minimize Stalls During Postsilicon Validation Ieee Transactions On Very Large Scale Integration Systems. 25: 1881-1894 |
| Aggarwal P, Sarangi SR. (2016) Lock-Free and Wait-Free Slot Scheduling Algorithms Ieee Transactions On Parallel and Distributed Systems. 27: 1387-1400 |
| Kalayappan R, Sarangi SR. (2015) FluidCheck: A redundant threading-based approach for reliable execution in manycore processors Acm Transactions On Architecture and Code Optimization. 12 |