Nastaran Baradaran, Ph.D.
Affiliations: | 2007 | Computer Science | University of Southern California, Los Angeles, CA, United States |
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"Nastaran Baradaran"Parents
Sign in to add mentor| Pedro C. Diniz | grad student | 2007 | USC | |
| (Compiler directed data management for configurable architectures with heterogeneous memory structures.) | ||||
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Publications
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| Baradaran N, Diniz PC. (2008) A compiler approach to managing storage and memory bandwidth in configurable architectures Acm Transactions On Design Automation of Electronic Systems. 13 |
| Baradaran N, Diniz PC. (2007) Exploiting parallelism in configurable architectures through custom array mapping Iet Computers and Digital Techniques. 1: 303-311 |
| Baradaran N, Diniz PC. (2006) Memory parallelism using custom array mapping to heterogeneous storage structures Proceedings - 2006 International Conference On Field Programmable Logic and Applications, Fpl. 383-388 |
| Baradaran N, Diniz PC. (2005) Compiler-directed design space exploration for caching and prefetching data in high-level synthesis Proceedings - 2005 Ieee International Conference On Field Programmable Technology. 2005: 233-240 |
| Baradaran N, Diniz PC. (2005) A register allocation algorithm in the presence of scalar replacement for fine-grain configurable architectures Proceedings -Design, Automation and Test in Europe, Date '05. 6-11 |
| Baradaran N, Diniz P. (2005) Exploiting data reuse in modern FPGAs: Opportunities and challenges for compilers Arc 2005 - International Workshop On Applied Reconfigurable Computing 2005. 1-10 |
| Baradaran N, Diniz PC, Park J. (2005) Extending the applicability of scalar replacement to multiple induction variables Lecture Notes in Computer Science. 3602: 455-469 |
| Baradaran N, Park J, Diniz PC. (2004) Data reuse in configurable architectures with RAM blocks Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 3203: 1113-1115 |
| Baradaran N, Park J, Diniz PC. (2004) Compiler reuse analysis for the mapping of data in FPGAs with RAM blocks Proceedings - 2004 Ieee International Conference On Field-Programmable Technology, Fpt '04. 145-152 |
| Baradaran N, Chame J, Chen C, et al. (2003) ECO: An empirical-based compilation and optimization system Proceedings - International Parallel and Distributed Processing Symposium, Ipdps 2003 |