Zhiliang Qian, Ph.D.
Affiliations: | 2014 | hkust | Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong |
Area:
Electronics and Electrical Engineering, Computer ScienceGoogle:
"Zhiliang Qian"Parents
Sign in to add mentor| Chi-Ying Tsui | grad student | 2014 | HKUST | |
| (High Performance Network-on-Chips (NoCs) Design: Performance Modeling, Routing Algorithm and Architecture Optimization.) | ||||
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Publications
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| Gao W, Qian Z, Zhou P. (2019) Reliability- and performance-driven mapping for regular 3D NoCs using a novel latency model and Simulated Allocation Integration. 65: 351-361 |
| Qian Z, Bogdan P, Tsui CY, et al. (2016) Performance evaluation of NoC-based multicore systems: From traffic analysis to NoC latency modeling Acm Transactions On Design Automation of Electronic Systems. 21 |
| Qian ZL, Juan DC, Bogdan P, et al. (2016) A Support Vector Regression (SVR)-based latency model for Network-on-Chip (NoC) architectures Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 471-484 |
| Zhu J, Qian Z, Tsui CY. (2016) BiLink: A high performance NoC router architecture using bi-directional link with double data rate Integration, the Vlsi Journal. 55: 30-42 |
| Qian Z, Abbas SM, Tsui CY. (2015) FSNoC: A flit-level speedup scheme for network on-chips using self-reconfigurable bidirectional channels Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 1854-1867 |