Ing-Chao Lin

Affiliations: 
2002-2007 Computer Science and Engineering Pennsylvania State University, State College, PA, United States 
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"Ing-Chao Lin"
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Lin I, Chang D, Chen W, et al. (2020) Global Clean Page First Replacement and Index-Aware Multistream Prefetcher in Hybrid Memory Architecture Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 1750-1763
Lin I, Chang D, Kao C, et al. (2019) Infection-Based Dead Page Prediction in Hybrid Memory Architecture Ieee Transactions On Very Large Scale Integration Systems. 27: 2401-2412
Chang D, Lin I, Lin Y, et al. (2019) OCMAS: Online Page Clustering for Multibank Scratchpad Memory Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 220-233
Luo J, Cheng H, Lin I, et al. (2019) TAP: Reducing the Energy of Asymmetric Hybrid Last-Level Cache via Thrashing Aware Placement and Migration Ieee Transactions On Computers. 68: 1704-1719
Lin I, Law YK, Xie Y. (2018) Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes Ieee Transactions On Very Large Scale Integration Systems. 26: 50-62
Chang D, Lin I, Yong L. (2017) ROHOM: Requirement-Aware Online Hybrid On-Chip Memory Management for Multicore Systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 357-369
Lin I, Chiou J. (2015) High-Endurance Hybrid Cache Design in CMP Architecture With Cache Partitioning and Access-Aware Policies Ieee Transactions On Very Large Scale Integration Systems. 23: 2149-2161
Lin IC, Yang YM, Lin CC. (2015) High-Performance Low-Power Carry Speculative Addition with Variable Latency Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 1591-1603
Lin IC, Cho YH, Yang YM. (2015) Aging-aware reliable multiplier design with adaptive hold logic Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 544-556
Lin I, Syu S, Ho T. (2014) NBTI tolerance and leakage reduction using gate sizing Acm Journal On Emerging Technologies in Computing Systems. 11: 4
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