| Year |
Citation |
Score |
| 2020 |
Li B, Doppa JR, Pande PP, Chakrabarty K, Qiu JX, Li H(. 3D-ReG: A 3D ReRAM-based Heterogeneous Architecture for Training Deep Neural Networks Acm Journal On Emerging Technologies in Computing Systems. 16: 1-24. DOI: 10.1145/3375699 |
0.324 |
|
| 2020 |
Musavvir S, Chatterjee A, Kim RG, Kim DH, Pande PP. Inter-Tier Process-Variation-Aware Monolithic 3-D NoC Design Space Exploration Ieee Transactions On Very Large Scale Integration Systems. 28: 686-699. DOI: 10.1109/Tvlsi.2019.2954770 |
0.474 |
|
| 2020 |
Hong W, Zhou Z, Nguyen B, Tang N, Kim J, Pande PP, Heo D. Analysis and Design Method of Multiple-Output Switched-Capacitor Voltage Regulators With a Reduced Number of Power Electronic Components Ieee Transactions On Circuits and Systems I-Regular Papers. 67: 3234-3247. DOI: 10.1109/Tcsi.2020.2989152 |
0.359 |
|
| 2020 |
Joardar BK, Doppa JR, Pande PP, Li H, Chakrabarty K. AccuReD: High Accuracy Training of CNNs on ReRAM/GPU Heterogeneous 3D Architecture Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2020.3013194 |
0.396 |
|
| 2019 |
Deshwal A, Jayakodi NK, Joardar BK, Doppa JR, Pande PP. MOOS: A Multi-Objective Design Space Exploration and Optimization Framework for NoC Enabled Manycore Systems Acm Transactions in Embedded Computing Systems. 18: 1-23. DOI: 10.1145/3358206 |
0.414 |
|
| 2019 |
Lee D, Das S, Doppa JR, Pande PP, Chakrabarty K. Impact of Electrostatic Coupling on Monolithic 3D-enabled Network on Chip Acm Transactions On Design Automation of Electronic Systems. 24: 62. DOI: 10.1145/3357158 |
0.45 |
|
| 2019 |
Hong W, Nguyen B, Zhou Z, Tang N, Kim J, Pande PP, Heo D. A Dual-Output Step-Down Switched-Capacitor Voltage Regulator With a Flying Capacitor Crossing Technique for Enhanced Power Efficiency Ieee Transactions On Very Large Scale Integration Systems. 27: 2861-2871. DOI: 10.1109/Tvlsi.2019.2930892 |
0.321 |
|
| 2019 |
Mandal SK, Bhat G, Patil CA, Doppa JR, Pande PP, Ogras UY. Dynamic Resource Management of Heterogeneous Mobile Platforms via Imitation Learning Ieee Transactions On Very Large Scale Integration Systems. 27: 2842-2854. DOI: 10.1109/Tvlsi.2019.2926106 |
0.395 |
|
| 2019 |
Joardar BK, Kim RG, Doppa JR, Pande PP, Marculescu D, Marculescu R. Learning-Based Application-Agnostic 3D NoC Design for Heterogeneous Manycore Systems Ieee Transactions On Computers. 68: 852-866. DOI: 10.1109/Tc.2018.2889053 |
0.493 |
|
| 2019 |
Lee D, Das S, Pande PP. Analyzing power-thermal-performance trade-offs in a high-performance 3D NoC architecture Integration. 65: 282-292. DOI: 10.1016/J.Vlsi.2017.12.002 |
0.417 |
|
| 2018 |
Lee D, Das S, Doppa JR, Pande PP, Chakrabarty K. Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip Acm Transactions On Design Automation of Electronic Systems. 23: 1-25. DOI: 10.1145/3223046 |
0.51 |
|
| 2018 |
Lee D, Das S, Kim DH, Doppa JR, Pande PP. Design Space Exploration of 3D Network-on-Chip Acm Journal On Emerging Technologies in Computing Systems. 14: 1-26. DOI: 10.1145/3197567 |
0.393 |
|
| 2018 |
Gopal S, Das S, Agarwal P, Ali SN, Heo D, Pande PP. High-Performance and Small-Form Factor Near-Field Inductive Coupling for 3-D NoC Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 26: 2921-2934. DOI: 10.1109/Tvlsi.2018.2865704 |
0.496 |
|
| 2018 |
Baylon J, Yu X, Gopal S, Molavi R, Mirabbasi S, Pande PP, Heo D. A 16-Gb/s Low-Power Inductorless Wideband Gain-Boosted Baseband Amplifier With Skewed Differential Topology for Wireless Network-on-Chip Ieee Transactions On Very Large Scale Integration Systems. 26: 2406-2418. DOI: 10.1109/Tvlsi.2018.2856890 |
0.484 |
|
| 2018 |
Li X, Duraisamy K, Bogdan P, Doppa JR, Pande PP. Scalable Network-on-Chip Architectures for Brain–Machine Interface Applications Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 26: 1895-1907. DOI: 10.1109/Tvlsi.2018.2843282 |
0.495 |
|
| 2018 |
Agarwal P, Kim J, Pande PP, Heo D. Zero-Power Feed-Forward Spur Cancelation for Supply-Regulated CMOS Ring PLLs Ieee Transactions On Very Large Scale Integration Systems. 26: 653-662. DOI: 10.1109/Tvlsi.2017.2788882 |
0.345 |
|
| 2018 |
Ali SN, Agarwal P, Renaud L, Molavi R, Mirabbasi S, Pande PP, Heo D. A 40% PAE Frequency-Reconfigurable CMOS Power Amplifier With Tunable Gate–Drain Neutralization for 28-GHz 5G Radios Ieee Transactions On Microwave Theory and Techniques. 66: 2231-2245. DOI: 10.1109/Tmtt.2018.2801806 |
0.426 |
|
| 2018 |
Jayakodi NK, Chatterjee A, Choi W, Doppa JR, Pande PP. Trading-Off Accuracy and Energy of Deep Inference on Embedded Systems: A Co-Design Approach Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 2881-2893. DOI: 10.1109/Tcad.2018.2857338 |
0.447 |
|
| 2018 |
Choi W, Duraisamy K, Kim RG, Doppa JR, Pande PP, Marculescu D, Marculescu R. On-Chip Communication Network for Efficient Training of Deep Convolutional Networks on Heterogeneous Manycore Systems Ieee Transactions On Computers. 67: 672-686. DOI: 10.1109/Tc.2017.2777863 |
0.511 |
|
| 2018 |
Gopal S, Agarwal P, Baylon J, Renaud L, Ali SN, Pande PP, Heo D. A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 8: 506-518. DOI: 10.1109/Jetcas.2018.2852624 |
0.446 |
|
| 2017 |
Das S, Lee D, Choi W, Doppa JR, Pande PP, Chakrabarty K. VFI-Based Power Management to Enhance the Lifetime of High-Performance 3D NoCs Acm Transactions On Design Automation of Electronic Systems. 23: 1-26. DOI: 10.1145/3092843 |
0.39 |
|
| 2017 |
Duraisamy K, Pande PP. Enabling High-Performance SMART NoC Architectures Using On-Chip Wireless Links Ieee Transactions On Very Large Scale Integration Systems. 25: 3495-3508. DOI: 10.1109/Tvlsi.2017.2748884 |
0.548 |
|
| 2017 |
Kim RG, Choi W, Chen Z, Doppa JR, Pande PP, Marculescu D, Marculescu R. Imitation Learning for Dynamic VFI Control in Large-Scale Manycore Systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 25: 2458-2471. DOI: 10.1109/Tvlsi.2017.2700726 |
0.446 |
|
| 2017 |
Agarwal P, Sah SP, Molavi R, Mirabbasi S, Pande PP, Oh SE, Kim J, Heo D. Switched Substrate-Shield-Based Low-Loss CMOS Inductors for Wide Tuning Range VCOs Ieee Transactions On Microwave Theory and Techniques. 65: 2964-2976. DOI: 10.1109/Tmtt.2017.2675423 |
0.316 |
|
| 2017 |
Das S, Doppa JR, Pande PP, Chakrabarty K. Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3-D Small-World Network-on-Chip Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 719-732. DOI: 10.1109/Tcad.2016.2604288 |
0.422 |
|
| 2017 |
Li X, Duraisamy K, Baylon J, Majumder T, Wei G, Bogdan P, Heo D, Pande PP. A Reconfigurable Wireless NoC for Large Scale Microbiome Community Analysis Ieee Transactions On Computers. 66: 1653-1666. DOI: 10.1109/Tc.2017.2706278 |
0.661 |
|
| 2016 |
Duraisamy K, Lu H, Pande PP, Kalyanaraman A. High-Performance and Energy-Efficient Network-on-Chip Architectures for Graph Analytics Acm Transactions On Embedded Computing Systems. 15: 1-26. DOI: 10.1145/2961027 |
0.504 |
|
| 2016 |
Duraisamy K, Xue Y, Bogdan P, Pande PP. Multicast-Aware High-Performance Wireless Network-on-Chip Architectures Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2016.2612647 |
0.567 |
|
| 2016 |
Li X, Duraisamy K, Bogdan P, Majumder T, Pande PP. Network-on-Chip-Enabled Multicore Platforms for Parallel Model Predictive Control Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2016.2528121 |
0.717 |
|
| 2016 |
Kim RG, Choi W, Chen Z, Pande PP, Marculescu D, Marculescu R. Wireless NoC and Dynamic VFI Codesign: Energy Efficiency Without Performance Penalty Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2015.2512611 |
0.492 |
|
| 2016 |
Mineo A, Palesi M, Ascia G, Pande PP, Catania V. On-Chip Communication Energy Reduction Through Reliability Aware Adaptive Voltage Swing Scaling Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1769-1782. DOI: 10.1109/Tcad.2016.2524556 |
0.429 |
|
| 2016 |
Kim RG, Choi W, Liu G, Mohandesi E, Pande PP, Marculescu D, Marculescu R. Wireless NoC for VFI-Enabled Multicore Chip Design: Performance Evaluation and Design Trade-Offs Ieee Transactions On Computers. 65: 1323-1336. DOI: 10.1109/Tc.2015.2441721 |
0.563 |
|
| 2016 |
Das S, Doppa JR, Kim DH, Pande PP, Chakrabarty K. Optimizing 3D NoC design for energy efficiency: A machine learning approach 2015 Ieee/Acm International Conference On Computer-Aided Design, Iccad 2015. 705-712. DOI: 10.1109/ICCAD.2015.7372639 |
0.324 |
|
| 2016 |
Pande PP, Kim RG, Choi W, Chen Z, Marculescu D, Marculescu R. The (low) power of less wiring: Enabling energy efficiency in many-core platforms through wireless NoC 2015 Ieee/Acm International Conference On Computer-Aided Design, Iccad 2015. 165-169. DOI: 10.1109/ICCAD.2015.7372565 |
0.538 |
|
| 2016 |
Pande PP. Introduction to special issue on International Green Computing Conference (IGCC) 2014 Sustainable Computing: Informatics and Systems. 11: 1-2. DOI: 10.1016/J.Suscom.2016.06.001 |
0.33 |
|
| 2016 |
Murray J, Wettin P, Pande PP, Shirazi B. Sustainable Wireless Network-on-Chip Architectures Sustainable Wireless Network-On-Chip Architectures. 1-155. |
0.477 |
|
| 2016 |
Das S, Doppa JR, Pande PP, Chakrabarty K. Reliability and performance trade-offs for 3D NoC-enabled multicore chips Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, Date 2016. 1429-1432. |
0.317 |
|
| 2015 |
Duraisamy K, Kim RG, Choi W, Liu G, Pande PP, Marculescu R, Marculescu D. Energy efficient MapReduce with VFI-enabled multicore platforms Proceedings - Design Automation Conference. 2015. DOI: 10.1145/2744769.2744835 |
0.428 |
|
| 2015 |
Das S, Lee D, Kim DH, Pande PP. Small-world network enabled energy efficient and robust 3D NoC architectures Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 20: 133-138. DOI: 10.1145/2742060.2742085 |
0.334 |
|
| 2015 |
Yu X, Rashtian H, Mirabbasi S, Pande PP, Heo D. An 18.7-Gb/s 60-GHz OOK Demodulator in 65-nm CMOS for Wireless Network-on-Chip Ieee Transactions On Circuits and Systems I: Regular Papers. DOI: 10.1109/Tcsi.2014.2386751 |
0.471 |
|
| 2015 |
Kim R, Murray J, Wettin P, Pande PP, Shirazi B. An energy-efficient millimeter-wave wireless NoC with congestion-aware routing and DVFS Proceedings - 2014 8th Ieee/Acm International Symposium On Networks-On-Chip, Nocs 2014. 192-193. DOI: 10.1109/NOCS.2014.7008789 |
0.454 |
|
| 2015 |
Murray J, Tang N, Pande PP, Heo D, Shirazi BA. DVFS pruning for wireless NoC architectures Ieee Design and Test. 32: 29-38. DOI: 10.1109/Mdat.2014.2357397 |
0.511 |
|
| 2015 |
Duraisamy K, Kim RG, Pande PP. Enhancing performance of wireless NoCs with distributed MAC protocols Proceedings - International Symposium On Quality Electronic Design, Isqed. 2015: 406-411. DOI: 10.1109/ISQED.2015.7085460 |
0.365 |
|
| 2015 |
Duraisamy K, Lu H, Pande PP, Kalyanaraman A. High performance and energy efficient wireless NoC-enabled multicore architectures for graph analytics 2015 International Conference On Compilers, Architecture and Synthesis For Embedded Systems, Cases 2015. 147-156. DOI: 10.1109/CASES.2015.7324555 |
0.388 |
|
| 2015 |
Majumder T, Pande PP, Kalyanaraman A. On-chip network-enabled many-core architectures for computational biology applications Proceedings -Design, Automation and Test in Europe, Date. 2015: 259-264. |
0.682 |
|
| 2014 |
Wettin P, Murray J, Kim R, Yu X, Pande PP, Heo D. Performance evaluation of wireless NoCs in presence of irregular network routing strategies Proceedings -Design, Automation and Test in Europe, Date. DOI: 10.7873/DATE2014.285 |
0.433 |
|
| 2014 |
Kim R, Liu G, Wettin P, Marculescu R, Marculescu D, Pande PP. Energy-efficient VFI-partitioned multicore design using wireless NoC architectures 2014 International Conference On Compilers, Architecture and Synthesis For Embedded Systems, Cases 2014. DOI: 10.1145/2656106.2656120 |
0.484 |
|
| 2014 |
Murray J, Kim R, Wettin P, Pande PP, Shirazi B. Performance evaluation of congestion-aware routing with DVFS on a millimeter-wave small-world wireless NoC Acm Journal On Emerging Technologies in Computing Systems. 11. DOI: 10.1145/2644816 |
0.47 |
|
| 2014 |
Murray J, Lu T, Wettin P, Pande PP, Shirazi B. Dual-level DVFS-enabled millimeter-wave wireless noc architectures Acm Journal On Emerging Technologies in Computing Systems. 10. DOI: 10.1145/2600074 |
0.565 |
|
| 2014 |
Chung H, Teuscher C, Pande P. Design and evaluation of technology-agnostic heterogeneous networks-on-chip Acm Journal On Emerging Technologies in Computing Systems. 10. DOI: 10.1145/2567666 |
0.547 |
|
| 2014 |
Yu X, Sah SP, Rashtian H, Mirabbasi S, Pande PP, Heo D. A 1.2-pJ/bit 16-Gb/s 60-GHz OOK Transmitter in 65-nm CMOS for Wireless Network-On-Chip Ieee Transactions On Microwave Theory and Techniques. DOI: 10.1109/Tmtt.2014.2347919 |
0.478 |
|
| 2014 |
Wettin P, Kim R, Murray J, Yu X, Pande PP, Ganguly A, Heoamlan D. Design space exploration for wireless NoCs incorporating irregular network routing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 1732-1745. DOI: 10.1109/Tcad.2014.2351577 |
0.658 |
|
| 2014 |
Yu X, Baylon J, Wettin P, Heo D, Pande PP, Mirabbasi S. Architecture and design of multichannel millimeter-wave wireless NoC Ieee Design and Test. 31: 19-28. DOI: 10.1109/Mdat.2014.2322995 |
0.413 |
|
| 2014 |
Pande PP, Kalyanaraman A. Guest editors' introduction: Hardware acceleration in computational biology Ieee Design and Test. 31: 6-7. DOI: 10.1109/Mdat.2013.2295761 |
0.358 |
|
| 2014 |
Majumder T, Pande PP, Kalyanaraman A. Hardware accelerators in computational biology: Application, potential, and challenges Ieee Design and Test. 31: 8-18. DOI: 10.1109/Mdat.2013.2290118 |
0.687 |
|
| 2014 |
Majumder T, Pande PP, Kalyanaraman A. Wireless NoC platforms with dynamic task allocation for maximum likelihood phylogeny reconstruction Ieee Design and Test. 31: 54-64. DOI: 10.1109/Mdat.2013.2288778 |
0.679 |
|
| 2014 |
Murray J, Wettin P, Kim R, Yu X, Pande PP, Shirazi B, Heo D. Thermal hotspot reduction in mm-Wave wireless NoC architectures Proceedings - International Symposium On Quality Electronic Design, Isqed. 645-652. DOI: 10.1109/ISQED.2014.6783388 |
0.441 |
|
| 2013 |
Wettin P, Vidapalapati A, Ganguly A, Pande PP. Complex network-enabled robust wireless network-on-chip architectures Acm Journal On Emerging Technologies in Computing Systems. 9. DOI: 10.1145/2491676 |
0.541 |
|
| 2013 |
Deb S, Chang K, Yu X, Sah SP, Cosic M, Ganguly A, Pande PP, Belzer B, Heo D. Design of an energy-efficient CMOS-compatible NoC architecture with millimeter-wave wireless interconnects Ieee Transactions On Computers. 62: 2382-2396. DOI: 10.1109/Tc.2012.224 |
0.738 |
|
| 2013 |
Sah SP, Yu X, Agarwal P, Rashtian H, Pande PP, Heo D, Mirabbasi S. A V-band wide locking-range injection-locked CMOS VCO for wireless network-on-chip receiver Ieee Mtt-S International Microwave Symposium Digest. DOI: 10.1109/MWSYM.2013.6697632 |
0.313 |
|
| 2013 |
Murray J, Hegde R, Lu T, Pande PP, Shirazi B. Sustainable dual-level DVFS-enabled NoC with on-chip wireless links Proceedings - International Symposium On Quality Electronic Design, Isqed. 135-143. DOI: 10.1109/ISQED.2013.6523601 |
0.459 |
|
| 2013 |
Majumder T, Pande PP, Kalyanaraman A. Network-on-chip with long-range wireless links for high-throughput scientific computation Proceedings - Ieee 27th International Parallel and Distributed Processing Symposium Workshops and Phd Forum, Ipdpsw 2013. 781-790. DOI: 10.1109/IPDPSW.2013.72 |
0.702 |
|
| 2013 |
Wettin P, Pande PP, Heo D, Belzer B, Deb S, Ganguly A. Design space exploration for reliable mm-wave wireless NoC architectures Proceedings of the International Conference On Application-Specific Systems, Architectures and Processors. 79-82. DOI: 10.1109/ASAP.2013.6567554 |
0.489 |
|
| 2013 |
Lu T, Pande PP, Shirazi B. A dynamic, compiler guided DVFS mechanism to achieve energy-efficiency in multi-core processors Sustainable Computing: Informatics and Systems. DOI: 10.1016/J.Suscom.2016.04.003 |
0.477 |
|
| 2013 |
Majumder T, Pande PP, Kalyanaraman A. High-throughput, energy-efficient network-on-chip-based hardware accelerators Sustainable Computing: Informatics and Systems. 3: 36-46. DOI: 10.1016/J.Suscom.2013.01.001 |
0.755 |
|
| 2013 |
Murray J, Lu T, Pande P, Shirazi B. Sustainable DVFS-Enabled Multi-Core Architectures with On-Chip Wireless Links Advances in Computers. 88: 125-158. DOI: 10.1016/B978-0-12-407725-6.00003-4 |
0.543 |
|
| 2013 |
Pande PP, Ganguly A, Chakrabarty K. Design technologies for green and sustainable computing systems Design Technologies For Green and Sustainable Computing Systems. 1-239. DOI: 10.1007/978-1-4614-4975-1 |
0.629 |
|
| 2012 |
Pande PP, Ganguly A. Introduction to the special issue on sustainable and green computing systems Acm Journal On Emerging Technologies in Computing Systems. 8. DOI: 10.1145/2367736.2367737 |
0.546 |
|
| 2012 |
Chang K, Deb S, Ganguly A, Yu X, Sah SP, Pande PP, Belzer B, Heo D. Performance evaluation and design trade-offs for wireless network-on-chip architectures Acm Journal On Emerging Technologies in Computing Systems. 8. DOI: 10.1145/2287696.2287706 |
0.756 |
|
| 2012 |
Majumder T, Borgens ME, Pande PP, Kalyanaraman A. On-chip network-enabled multicore platforms targeting maximum likelihood phylogeny reconstruction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1061-1073. DOI: 10.1109/Tcad.2012.2188401 |
0.709 |
|
| 2012 |
Majumder T, Sarkar S, Pande PP, Kalyanaraman A. NoC-based hardware accelerator for breakpoint phylogeny Ieee Transactions On Computers. 61: 857-869. DOI: 10.1109/Tc.2011.100 |
0.691 |
|
| 2012 |
Murray J, Pande PP, Shirazi B. DVFS-enabled sustainable wireless NoC architecture International System On Chip Conference. 301-306. DOI: 10.1109/SOCC.2012.6398326 |
0.487 |
|
| 2012 |
Deb S, Ganguly A, Pande PP, Belzer B, Heo D. Wireless NoC as interconnection backbone for multicore chips: Promises and challenges Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 2: 228-239. DOI: 10.1109/Jetcas.2012.2193835 |
0.75 |
|
| 2011 |
Ganguly A, Chang K, Deb S, Pande PP, Belzer B, Teuscher C. Scalable hybrid wireless network-on-chip architectures for multicore systems Ieee Transactions On Computers. 60: 1485-1502. DOI: 10.1109/Tc.2010.176 |
0.749 |
|
| 2011 |
Yu X, Sah SP, Deb S, Pande PP, Belzer B, Heo D. A wideband body-enabled millimeter-wave transceiver for wireless network-on-chip Midwest Symposium On Circuits and Systems. DOI: 10.1109/MWSCAS.2011.6026282 |
0.367 |
|
| 2010 |
Marculescu R, Teuscher C, Pande PP. Unconventional fabrics, architectures, and models for future multi-core systems 2010 Ieee/Acm/Ifip International Conference On Hardware/Software Codesign and System Synthesis, Codes+Isss 2010. 327-328. DOI: 10.1145/1878961.1879017 |
0.461 |
|
| 2010 |
Sarkar S, Kulkarni GR, Pande PP, Kalyanaraman A. Network-on-chip hardware accelerators for biological sequence alignment Ieee Transactions On Computers. 59: 29-41. DOI: 10.1109/Tc.2009.133 |
0.496 |
|
| 2010 |
Pande PP, Vangal S. Guest editors' introduction: Promises and challenges of novel interconnect technologies Ieee Design and Test of Computers. 27: 6-8. DOI: 10.1109/Mdt.2010.87 |
0.478 |
|
| 2010 |
Sarkar S, Majumder T, Kalyanaraman A, Pande PP. Hardware accelerators for biocomputing: A survey Iscas 2010 - 2010 Ieee International Symposium On Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 3789-3792. DOI: 10.1109/ISCAS.2010.5537736 |
0.663 |
|
| 2009 |
Pande PP, Ganguly A, Chang K, Teuscher C. Hybrid wireless network on chip: A new paradigm in multi-core design 2nd International Workshop On Network On Chip Architectures, Nocarc 2009, in Conjunction With the 42nd Annual Ieee/Acm International Symposium On Microarchitecture, Micro42. 71-76. DOI: 10.1145/1645213.1645230 |
0.493 |
|
| 2009 |
Ganguly A, Pande PP, Belzer B. Crosstalk-aware channel coding schemes for energy efficient and reliable NOC interconnects Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 1626-1639. DOI: 10.1109/Tvlsi.2008.2005722 |
0.623 |
|
| 2009 |
Feero BS, Pande PP. Networks-on-chip in a three-dimensional environment: A performance evaluation Ieee Transactions On Computers. 58: 32-45. DOI: 10.1109/Tc.2008.142 |
0.492 |
|
| 2009 |
Ganguly A, Chang K, Pande PP, Belzer B, Nojeh A. Performance evaluation of wireless networks on chip architectures Proceedings of the 10th International Symposium On Quality Electronic Design, Isqed 2009. 350-355. DOI: 10.1109/ISQED.2009.4810319 |
0.473 |
|
| 2008 |
Grecu C, Ivanov A, Saleh R, Pande PP, Rusu C, Anghel L, Nuca V. A flexible network-on-chip simulator for early design space exploration 1st Microsystems and Nanoelectronics Research Conference, Mnrc 2008 - Enabling Synergy and Accelerating Excellence in Graduate Student Research. 33-36. DOI: 10.1109/MNRC.2008.4683371 |
0.423 |
|
| 2008 |
Pande PP, Ganguly A, Belzer B, Nojeh A, Ivanov A. Novel interconnect infrastructures for massive multicore chips - An overview Proceedings - Ieee International Symposium On Circuits and Systems. 2777-2780. DOI: 10.1109/ISCAS.2008.4542033 |
0.349 |
|
| 2008 |
Pande PP, Ganguly A, Zhu H, Grecu C. Energy reduction through crosstalk avoidance coding in networks on chip Journal of Systems Architecture. 54: 441-451. DOI: 10.1016/J.Sysarc.2007.09.002 |
0.656 |
|
| 2008 |
Ganguly A, Pande PP, Belzer B, Grecu C. Design of low power & reliable networks on chip through joint crosstalk avoidance and multiple error correction coding Journal of Electronic Testing: Theory and Applications (Jetta). 24: 67-81. DOI: 10.1007/S10836-007-5035-1 |
0.604 |
|
| 2007 |
Grecu C, Ivanov A, Saleh R, Pande PP. Testing network-on-chip communication fabrics Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 2201-2213. DOI: 10.1109/Tcad.2007.907263 |
0.383 |
|
| 2007 |
Nyathi J, Sarkar S, Pande PP. Multiple clock domain synchronization for network on chip architectures Proceedings - 20th Anniversary Ieee International Soc Conference. 291-294. DOI: 10.1109/SOCC.2007.4545477 |
0.444 |
|
| 2007 |
Pande PP, Zhu H, Ganguly A, Grecu C. Crosstalk-aware energy reduction in NoC communication fabrics 2006 Ieee International Systems-On-Chip Conference, Soc. 225-228. DOI: 10.1109/SOCC.2006.283886 |
0.353 |
|
| 2007 |
Feero B, Pande PP. Performance evaluation for three-dimensional networks-on-chip Proceedings - Ieee Computer Society Annual Symposium On Vlsi: Emerging Vlsi Technologies and Architectures. 305-310. DOI: 10.1109/ISVLSI.2007.79 |
0.356 |
|
| 2007 |
Ganguly A, Pande PP, Belzer B, Grecu C. Addressing signal integrity in networks on chip interconnects through crosstalk-aware double error correction coding Proceedings - Ieee Computer Society Annual Symposium On Vlsi: Emerging Vlsi Technologies and Architectures. 317-322. DOI: 10.1109/ISVLSI.2007.21 |
0.389 |
|
| 2007 |
Pande PP, Ganguly A, Feero B, Grecu C. Applicability of energy efficient coding methodology to address signal integrity in 3D NoC fabrics Proceedings - Iolts 2007 13th Ieee International On-Line Testing Symposium. 161-166. DOI: 10.1109/IOLTS.2007.18 |
0.305 |
|
| 2006 |
Saleh R, Wilton S, Mirabbasi S, Hu A, Greenstreet M, Lemieux G, Pande PP, Grecu C, Ivanov A. System-on-chip: Reuse and integration Proceedings of the Ieee. 94: 1050-1068. DOI: 10.1109/JPROC.2006.873611 |
0.406 |
|
| 2006 |
Pande PP, Haibo Z, Ganguly A, Grecu C. Energy reduction through crosstalk avoidance coding in NoC paradigm Proceedings of the 9th Euromicro Conference On Digital System Design: Architectures, Methods and Tools, Dsd 2006. 689-695. DOI: 10.1109/DSD.2006.49 |
0.427 |
|
| 2006 |
Grecu C, Ivanov A, Saleh R, Pande PP. NoC interconnect yield improvement using crosspoint redundancy Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 457-465. DOI: 10.1109/DFT.2006.46 |
0.323 |
|
| 2006 |
Pande PP, Ganguly A, Feero B, Belzer B, Grecu C. Design of low power & reliable networks on chip through joint crosstalk avoidance and forward error correction coding Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 466-474. DOI: 10.1109/DFT.2006.22 |
0.409 |
|
| 2005 |
Pande PP, Grecu C, Jones M, Ivanov A, Saleh R. Performance evaluation and design trade-offs for network-on-chip interconnect architectures Ieee Transactions On Computers. 54: 1025-1040. DOI: 10.1109/Tc.2005.134 |
0.528 |
|
| 2005 |
Pande PP, Grecu C, Ivanov A, Saleh R, De Micheli G. Design, synthesis, and test of networks on chips Ieee Design and Test of Computers. 22: 404-413. DOI: 10.1109/Mdt.2005.108 |
0.479 |
|
| 2005 |
Pande PP, Grecu C, Jones M, Ivanov A, Saleh R. Effect of traffic localization on energy dissipation in NoC-based interconnect Proceedings - Ieee International Symposium On Circuits and Systems. 1774-1777. DOI: 10.1109/ISCAS.2005.1464952 |
0.356 |
|
| 2005 |
Grecu C, Pande PP, Ivanov A, Saleh R. Timing analysis of network on chip architectures for MP-SoC platforms Microelectronics Journal. 36: 833-845. DOI: 10.1016/j.mejo.2005.03.006 |
0.469 |
|
| 2005 |
Pande PP, Grecu C, Ivanov A, Saleh R. Destination network-on-chip Electronic Engineering Times. 6-7. |
0.458 |
|
| 2004 |
Pande PP, Grecu C, Jones M, Ivanov A, Saleh R. Evaluation of MP-SoC interconnect architectures: A case study Proceedings - 4th Ieee International Workshop On System-On-Chip For Real-Time Applications, Iwsoc 2004. 253-256. DOI: 10.1109/IWSOC.2004.1319889 |
0.401 |
|
| 2004 |
Grecu C, Pande PP, Ivanov A, Saleh R. A scalable communication-centric SoC interconnect architecture Proceedings - 5th International Symposium On Quality Electronic Design, Isqued 2004. 343-348. DOI: 10.1109/ISQED.2004.1283698 |
0.421 |
|
| 2004 |
Grecu C, Pande PP, Ivanov A, Saleh R. Structured interconnect architecture: A solution for the non-scalability of bus-based SoCs Proceedings of the Acm Great Lakes Symposium On Vlsi. 192-195. |
0.396 |
|
| 2003 |
Pande PP, Grecu C, Ivanov A, Saleh R. Switch-based interconnect architecture for future systems on chip Proceedings of Spie - the International Society For Optical Engineering. 5117: 228-237. DOI: 10.1117/12.498809 |
0.525 |
|
| 2003 |
Pande PP, Grecu C, Ivanov A, Saleh R. High-throughput switch-based interconnect for future SoCs Proceedings - 3rd Ieee International Workshop On System-On-Chip For Real-Time Applications, Iwsoc 2003. 304-310. DOI: 10.1109/IWSOC.2003.1213053 |
0.424 |
|
| 2003 |
Pande PP, Grecu C, Ivanov A, Saleh R. Design of a switch for network on chip applications Proceedings - Ieee International Symposium On Circuits and Systems. 5. |
0.416 |
|
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