S Simon Wong
Affiliations: | Electrical Engineering | Stanford University, Palo Alto, CA |
Website:
https://profiles.stanford.edu/s-simon-wongGoogle:
"Siu-Weng Simon Wong" OR "S Simon Wong"Bio:
https://www2.eecs.berkeley.edu/Pubs/Dissertations/Years/1983.html Thin Gate Dielectrics for MOSFETs Siu-Weng S. Wong [advisor: William G. Oldham]
Parents
Sign in to add mentor| William G. Oldham | grad student | 1983 | UC Berkeley | |
| (Thin Gate Dielectrics for MOSFETs) | ||||
Children
Sign in to add trainee| Bendik Kleveland | grad student | 2000 | Stanford |
| Haebum Lee | grad student | 2001 | Stanford |
| Theerachet Soorapanth | grad student | 2002 | Stanford |
| Dae-Yong Kim | grad student | 2004 | Stanford |
| Frank P. O'Mahony | grad student | 2004 | Stanford |
| Niranjan Talwalkar | grad student | 2004 | Stanford |
| Haitao Gan | grad student | 2006 | Stanford |
| Aaron M. Gibby | grad student | 2008 | Stanford |
| Hyunwoo Nho | grad student | 2008 | Stanford |
BETA: Related publications
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Publications
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| Jiang Z, Qin S, Li H, et al. (2019) Next-Generation Ultrahigh-Density 3-D Vertical Resistive Switching Memory (VRSM)—Part II: Design Guidelines for Device, Array, and Architecture Ieee Transactions On Electron Devices. 66: 5147-5154 |
| Lee EH, Wong SS. (2017) Analysis and Design of a Passive Switched-Capacitor Matrix Multiplier for Approximate Computing Ieee Journal of Solid-State Circuits. 52: 261-271 |
| Zhang Z, Gao B, Fang Z, et al. (2015) All-Metal-Nitride RRAM Devices Ieee Electron Device Letters. 36: 29-31 |
| Yeh CWS, Wong SS. (2015) Compact One-Transistor-N-RRAM Array Architecture for Advanced CMOS Technology Ieee Journal of Solid-State Circuits |
| Fang Z, Wang XP, Sohn J, et al. (2014) The role of ti capping layer in HfOx-Based RRAM Devices Ieee Electron Device Letters. 35: 912-914 |
| Park J, Oh S, Kim S, et al. (2013) Impact of III–V and Ge Devices on Circuit Performance Ieee Transactions On Very Large Scale Integration Systems. 21: 1189-1200 |
| Zhang Z, Chen CY, Crnogorac F, et al. (2013) Low-temperature monolithic three-layer 3-D process for FPGA Ieee Electron Device Letters. 34: 1044-1046 |
| Zhang Z, Wu Y, Wong H-P, et al. (2013) Nanometer-Scale ${\rm HfO}_{x}$ RRAM Ieee Electron Device Letters. 34: 1005-1007 |
| Ou E, Wong SS. (2011) Array architecture for a nonvolatile 3-dimensional cross-point resistance-change memory Ieee Journal of Solid-State Circuits. 46: 2158-2170 |
| Crnogorac F, Wong S, Pease RFW. (2010) Semiconductor crystal islands for three-dimensional integration Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena. 28 |