Subramanian S. Iyer
Affiliations: | 2015 | IBM Systems and Technology Group | |
| 2015- | Electrical Engineering | University of California, Los Angeles, Los Angeles, CA |
Area:
System Scaling Technology, advanced packaging and 3D integration, technologies and techniques for the memory subsystem integration and neuromorphic computingWebsite:
https://www.ee.ucla.edu/subramanian-s-iyer/Google:
"Subramanian Iyer"Bio:
https://www.chips.ucla.edu/chips-summary
https://www.proquest.com/openview/e6d6b9036f7ea235a11b467c2e8a846a/1
https://www.chips.ucla.edu/page/Theses%20and%20Dissertations
Parents
Sign in to add mentor| Frederick Graham Allen | grad student | 1981 | UCLA (Physics Tree) | |
| (Dopant Incorporation in Silicon Molecular Beam Epitaxy) | ||||
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Publications
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| Iyer SS, Jangam S, Vaisband B. (2019) Silicon interconnect fabric: A versatile heterogeneous integration platform for AI systems Journal of Reproduction and Development. 63 |
| Gupta P, Iyer SS. (2019) Goodbye, motherboard. Bare chiplets bonded to silicon will make computers smaller and more powerful: Hello, silicon-interconnect fabric Ieee Spectrum. 56: 28-33 |
| Khan F, Han MS, Moy D, et al. (2019) Design Optimization and Modeling of Charge Trap Transistors (CTTs) in 14 nm FinFET Technologies Ieee Electron Device Letters. 40: 1100-1103 |
| Fukushima T, Alam A, Hanna A, et al. (2018) Flexible Hybrid Electronics Technology Using Die-First FOWLP for High-Performance and Scalable Heterogeneous System Integration Ieee Transactions On Components, Packaging and Manufacturing Technology. 8: 1738-1746 |
| Zhu L, Badr Y, Wang S, et al. (2017) Assessing Benefits of a Buried Interconnect Layer in Digital Designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 346-350 |
| Khan F, Cartier E, Woo JCS, et al. (2017) Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- $k$ -Metal-Gate CMOS Technologies Ieee Electron Device Letters. 38: 44-47 |
| Iyer SS. (2016) Heterogeneous Integration for Performance and Scaling Ieee Transactions On Components, Packaging and Manufacturing Technology |
| Kirihata T, Golz J, Wordeman M, et al. (2016) Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias Ieee Journal On Emerging and Selected Topics in Circuits and Systems |
| Fredeman G, Plass DW, Mathews A, et al. (2015) A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access Ieee Journal of Solid-State Circuits |
| Kasanaboina PK, Ahmad E, Li J, et al. (2015) Self-catalyzed growth of dilute nitride GaAs/GaAsSbN/GaAs core-shell nanowires by molecular beam epitaxy Applied Physics Letters. 107 |