Nagendra Krishnapura, Ph.D.
Affiliations: | 2000 | Columbia University, New York, NY |
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"Nagendra Krishnapura"Parents
Sign in to add mentor| Yannis Tsividis | grad student | 2000 | Columbia | |
| (Large dynamic range dynamically biased log -domain filters.) | ||||
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Publications
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| Kumar RSA, Krishnapura N. (2020) Multi-Channel Analog-to-Digital Conversion Techniques Using a Continuous-Time Delta-Sigma Modulator Without Reset Ieee Transactions On Circuits and Systems I-Regular Papers. 1-11 |
| Chithra, Krishnapura N. (2020) A Flexible 18-Channel Multi-Hit Time-to-Digital Converter for Trigger-Based Data Acquisition Systems Ieee Transactions On Circuits and Systems. 67: 1892-1901 |
| Praveen MV, Krishnapura N. (2020) High Linearity Transmit Power Mixers Using Baseband Current Feedback Ieee Journal of Solid-State Circuits. 55: 272-281 |
| Bhat A, Krishnapura N. (2019) On-Chip Static Phase Difference Measurement Circuit With Gain and Offset Calibration Ieee Transactions On Circuits and Systems Ii-Express Briefs. 66: 162-166 |
| Kumar S, Goroju R, Bhat DK, et al. (2019) Design Considerations for Low-Distortion Filter and Oscillator ICs for Testing High-Resolution ADCs Ieee Transactions On Circuits and Systems I-Regular Papers. 66: 3393-3401 |
| Krishnapura N, Bhat AN, Mukherjee S, et al. (2019) Maximizing the Data Rate of an Inductively Coupled Chip-to-Chip Link by Resetting the Channel State Variables Ieee Transactions On Circuits and Systems I-Regular Papers. 66: 3531-3543 |
| Kumar RSA, Behera D, Krishnapura N. (2018) Reset-Free Memoryless Delta–Sigma Analog-to-Digital Conversion Ieee Transactions On Circuits and Systems I-Regular Papers. 65: 3651-3661 |
| Mondal I, Krishnapura N. (2018) Expansion and Compression of Analog Pulses by Bandwidth Scaling of Continuous-Time Filters Ieee Transactions On Circuits and Systems I-Regular Papers. 65: 2703-2714 |
| Bhat A, Krishnapura N. (2018) Low $1/f^{3}$ Phase Noise Quadrature LC VCOs Ieee Transactions On Circuits and Systems I-Regular Papers. 65: 2127-2138 |
| Mondal I, Krishnapura N. (2017) A 2-GHz Bandwidth, 0.25–1.7 ns True-Time-Delay Element Using a Variable-Order All-Pass Filter Architecture in 0.13 $\mu$ m CMOS Ieee Journal of Solid-State Circuits. 52: 2180-2193 |