Yun Chiu, Ph.D.
Affiliations: | 2004 | University of California, Berkeley, Berkeley, CA, United States |
Area:
Design, Modeling and Analysis (DMA); Integrated Circuits (INC)Google:
"Yun Chiu"Parents
Sign in to add mentor| Paul R. Gray | grad student | 2004 | UC Berkeley | |
| (High-performance pipeline A/D converter design in deep-submicron CMOS.) | ||||
Children
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Publications
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| Li Y, Zhou Y, Chiu Y. (2020) A Compact Calibration Model for Linearizing CMOS Sample-and-Hold Circuits Ieee Transactions On Circuits and Systems Ii-Express Briefs. 1-1 |
| Zhou Y, Xu B, Chiu Y. (2019) A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC Ieee Journal of Solid-State Circuits. 54: 2207-2218 |
| Xu H, Huang H, Cai Y, et al. (2019) A 78.5-dB SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS Ieee Journal of Solid-State Circuits. 54: 441-451 |
| Wu B, Zhu S, Zhou Y, et al. (2018) A 9-bit 215 MS/s Folding-Flash Time-to-Digital Converter Based on Redundant Remainder Number System in 45-nm CMOS Ieee Journal of Solid-State Circuits. 53: 839-849 |
| Zhu S, Wu B, Cai Y, et al. (2018) A 2-GS/s 8-bit Non-Interleaved Time-Domain Flash ADC Based on Remainder Number System in 65-nm CMOS Ieee Journal of Solid-State Circuits. 53: 1172-1183 |
| Huang H, Xu H, Elies B, et al. (2017) A Non-Interleaved 12-b 330-MS/s Pipelined-SAR ADC With PVT-Stabilized Dynamic Amplifier Achieving Sub-1-dB SNDR Variation Ieee Journal of Solid-State Circuits. 52: 3235-3247 |
| Xu B, Zhou Y, Chiu Y. (2017) A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS Ieee Journal of Solid-State Circuits. 52: 1091-1100 |
| Naquin C, Cai Y, Hu G, et al. (2017) Application of a Quantum-Well Silicon NMOS Transistor as a Folding Amplifier Frequency Multiplier Ieee Journal of the Electron Devices Society. 5: 224-231 |
| Huang H, Du L, Chiu Y. (2016) A 1.2-GS/s 8-bit two-step SAR ADC in 65-nm CMOS with passive residue transfer 2015 Ieee Asian Solid-State Circuits Conference, a-Sscc 2015 - Proceedings |
| Wu B, Zhu S, Xu B, et al. (2016) A 24.7 mW 65 nm CMOS SAR-Assisted CT Δ Σ Modulator With Second-Order Noise Coupling Achieving 45 MHz Bandwidth and 75.3 dB SNDR Ieee Journal of Solid-State Circuits |