Nick Lindert, Ph.D.
Affiliations: | 2001 | University of California, Berkeley, Berkeley, CA, United States |
Area:
Semiconductor Device TechnologiesGoogle:
"Nick Lindert"Parents
Sign in to add mentor| Chenming Hu | grad student | 2001 | UC Berkeley | |
| (Process development and device design for continued MOSFET scaling.) | ||||
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Publications
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| Hamzaoglu F, Arslan U, Bisnik N, et al. (2015) A 1 Gb 2 GHz 128 GB/s bandwidth embedded DRAM in 22 nm tri-gate CMOS technology Ieee Journal of Solid-State Circuits. 50: 150-157 |
| Hamzaoglu F, Arslan U, Bisnik N, et al. (2014) 13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 57: 230-231 |
| Wang Y, Arslan U, Bisnik N, et al. (2013) Retention time optimization for eDRAM in 22nm tri-gate CMOS technology Technical Digest - International Electron Devices Meeting, Iedm. 9.5.1-9.5.4 |
| Brain R, Baran A, Bisnik N, et al. (2013) A 22nm high performance embedded DRAM SoC technology featuring tri-gate transistors and MIMCAP COB Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. T16-T17 |
| Van Der Voorn P, Agostinelli M, Choi SJ, et al. (2010) A 32nm low power RF CMOS SOC technology featuring high-k/metal gate Digest of Technical Papers - Symposium On Vlsi Technology. 137-138 |
| Jan CH, Bai P, Biswas S, et al. (2008) A 45nm low power system-on-chip technology with dual gate (Logic and I/O) high-k/ metal gate strained silicon transistors Technical Digest - International Electron Devices Meeting, Iedm |
| Post I, Akbar M, Curello G, et al. (2006) A 65nm CMOS SOC technology featuring strained silicon transistors for RF applications Technical Digest - International Electron Devices Meeting, Iedm |
| Tyagi S, Auth C, Bai P, et al. (2005) An advanced low power, high performance, strained channel 65nm technology Technical Digest - International Electron Devices Meeting, Iedm. 2005: 245-247 |
| Jan CH, Bai P, Choi J, et al. (2005) A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors Technical Digest - International Electron Devices Meeting, Iedm. 2005: 60-63 |
| Bai P, Auth C, Balakrishnan S, et al. (2004) A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm2 SRAM cell Technical Digest - International Electron Devices Meeting, Iedm. 657-660 |