Scott J. Weber, Ph.D.
Affiliations: | 2005 | University of California, Berkeley, Berkeley, CA, United States |
Area:
Computer Architecture & Engineering (ARC); Design, Modeling and Analysis (DMA); Scientific Computing (SCI)Google:
"Scott Weber"Parents
Sign in to add mentor| Kurt Keutzer | grad student | 2005 | UC Berkeley | |
| (TIPI: Tiny Instruction Processors and Interconnect.) | ||||
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Publications
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| Mihal A, Weber S, Keutzer K. (2007) Sub-RISC processors Customizable Embedded Processors. 303-336 |
| Shah N, Plishker W, Ravindran K, et al. (2005) Successfully deploying the ASIP Building Asips: the Mescal Methodology. 179-225 |
| Weber S, Jin Y, Gries M, et al. (2005) Efficiently describing and evaluating the ASIPs Building Asips: the Mescal Methodology. 85-130 |
| Weber SJ, Moskewicz MW, Gries M, et al. (2004) Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures Second Ieee/Acm/Ifip International Conference On Hardware/Software Codesign and Systems Synthesis, Codes+Isss 2004. 18-23 |
| Sauer C, Gries M, Gomez JI, et al. (2004) Developing a flexible interface for RapidIO, hypertransport, and PCI-express International Conference On Parallel Computing in Electrical Engineering: Workshop On System Design Automation, Sda, Parelec 2004. 129-134 |
| Mihal A, Kulkarni C, Moskewicz M, et al. (2002) Developing architectural platforms: A disciplined approach Ieee Design and Test of Computers. 19: 6-16 |
| Tasiran S, Fallah F, Chinnery DG, et al. (2001) A functional validation technique: Biased-random simulation guided by observability-based coverage Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 82-88 |