David G. Chinnery, Ph.D.

Affiliations: 
2006 University of California, Berkeley, Berkeley, CA, United States 
Area:
Computer Architecture & Engineering (ARC); Design, Modeling and Analysis (DMA); Scientific Computing (SCI)
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"David Chinnery"

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Kurt Keutzer grad student 2006 UC Berkeley
 (Low power design automation.)
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Publications

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Sharma A, Chinnery D, Reimann T, et al. (2020) Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 1456-1469
Sharma A, Chinnery D, Bhardwaj S, et al. (2016) Fast Lagrangian Relaxation based gate sizing using multi-threading 2015 Ieee/Acm International Conference On Computer-Aided Design, Iccad 2015. 426-433
Chinnery D. (2013) High performance and low power design techniques for ASIC and custom in nanometer technologies Proceedings of the International Symposium On Physical Design. 25-32
Chinnery D, Keutzer K. (2007) Linear programming for multi-Vth and multi-Vdd assignment Closing the Power Gap Between Asic and Custom: Tools and Techniques For Low Power Design. 151-188
Chinnery D, Keutzer K. (2007) Linear programming for gate sizing Closing the Power Gap Between Asic and Custom: Tools and Techniques For Low Power Design. 121-149
Chinnery D, Keutzer K. (2007) Voltage scaling Closing the Power Gap Between Asic and Custom: Tools and Techniques For Low Power Design. 90-106
Chinnery D, Keutzer K. (2007) Pipelining to reduce the power Closing the Power Gap Between Asic and Custom: Tools and Techniques For Low Power Design. 55-88
Chinnery D, Keutzer K. (2007) Overview of the factors affecting the power consumption Closing the Power Gap Between Asic and Custom: Tools and Techniques For Low Power Design. 11-53
Chinnery D, Keutzer K. (2007) Introduction Closing the Power Gap Between Asic and Custom: Tools and Techniques For Low Power Design. 1-10
Chinnery D, Keutzer K. (2007) Preface Closing the Power Gap Between Asic and Custom: Tools and Techniques For Low Power Design. v-vi
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