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Kedar K. Patel, Ph.D.

Affiliations: 
2010 Electrical Engineering & Computer Sciences University of California, Berkeley, Berkeley, CA, United States 
Area:
Energy (ENE); Integrated Circuits (INC); Physical Electronics (PHY); Semiconductor manufacturing; Solid-State Devices
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Costas J. Spanos grad student 2010 UC Berkeley
 (Intrinsic and systematic variability in nanometer CMOS technologies.)

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Publications

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Patel K, Wallow T, Levinson HJ, et al. (2010) Comparative study of line width roughness (LWR) in next-generation lithography (NGL) processes Proceedings of Spie - the International Society For Optical Engineering. 7640
Patel K, Lahiri SN, Spanos CJ. (2010) Robust estimation of line width roughness parameters Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics. 28: C6H18-C6H33
Patel K, Liu TJK, Spanos C. (2008) Impact of gate line edge roughness on double-gate FinFET performance variability Proceedings of Spie - the International Society For Optical Engineering. 6925
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