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Ganapathy Parthasarathy, Ph.D.

Affiliations: 
2005 University of California, Santa Barbara, Santa Barbara, CA, United States 
Area:
Computer Engineering
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Kwang-Ting (Tim) Cheng grad student 2005 UC Santa Barbara
 (Hybrid methods for satisfiability checking in register -transfer level circuits.)

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Parthasarathy G, Iyer MK, Cheng KT, et al. (2005) RTL SAT simplification by Boolean and interval arithmetic reasoning Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 297-302
Lu F, Iyer MK, Parthasarathy G, et al. (2005) An efficient sequential SAT solver with improved search strategies Proceedings -Design, Automation and Test in Europe, Date '05. 1102-1107
Iyer MK, Parthasarathy G, Cheng KT. (2005) Efficient conflict-based learning in an RTL circuit constraint solver Proceedings -Design, Automation and Test in Europe, Date '05. 666-671
Parthasarathy G, Iyer MK, Cheng KT, et al. (2005) Structural search for RTL with predicate learning Proceedings - Design Automation Conference. 451-456
Parthasarathy G, Iyer MK, Cheng KTT, et al. (2004) Safety property verification using sequential SAT and bounded model checking Ieee Design and Test of Computers. 21: 132-143
Parthasarathy G, Iyer MK, Cheng KT, et al. (2004) An efficient finite-domain constraint solver for circuits Proceedings - Design Automation Conference. 212-217
Parthasarathy G, Iyer MK, Cheng KT, et al. (2004) Efficient reachability checking using sequential SAT Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 418-423
Parthasarathy G, Iyer MK, Cheng KT, et al. (2003) A comparison of BDDs, BMC, and sequential SAT for model checking Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 2003: 157-162
Iyer MK, Parthasarathy G, Cheng KT. (2003) SATORI - A fast sequential sat engine for circuits Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 320-325
Parthasarathy G, Iyer MK, Feng T, et al. (2002) Combining ATPG and symbolic simulation for efficient validation of embedded array systems Ieee International Test Conference (Tc). 203-212
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