Earl E. Swartzlander, Jr.
Affiliations: | 1990- | Electrical and Computer Engineering | University of Texas at Austin, Austin, Texas, U.S.A. |
Area:
Electronics and Electrical EngineeringWebsite:
https://www.ece.utexas.edu/people/faculty/earl-swartzlanderGoogle:
"Earl Eugene Swartzlander" OR "Earl E. Swartzlander"Bio:
https://ieeexplore.ieee.org/author/37273356600
https://orcid.org/0000-0002-8699-5277
https://utdirect.utexas.edu/apps/student/coursedocs/nlogon/download/7196607/
https://www.computingreviews.com/masthead/masthead.cfm?editor=swartz
https://www.researchgate.net/profile/Earl-Jr
https://www.proquest.com/openview/45ddd2b7affacea2319bfcf5a9d8e3be/1.pdf
Children
Sign in to add trainee| K'Andrea C. Bickerstaff | grad student | 2007 | UT Austin |
| Hani H. Saleh | grad student | 2009 | UT Austin |
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Publications
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| Liu W, Cao T, Yin P, et al. (2019) Design and Analysis of Approximate Redundant Binary Multipliers Ieee Transactions On Computers. 68: 804-819 |
| Liu W, Mei F, Wang C, et al. (2018) Data Compression Device Based on Modified LZ4 Algorithm Ieee Transactions On Consumer Electronics. 64: 110-117 |
| Liu W, Swartzlander EE, Oneill M. (2017) Guest Editorial: Introduction to the Special Issue on Emerging Technologies and Designs for Application-Specific Computing Ieee Transactions On Emerging Topics in Computing. 5: 148-150 |
| Chang Y, Zhou F, Fowler BW, et al. (2017) Memcomputing (Memristor + Computing) in Intrinsic SiO x -Based Resistive Switching Memory: Arithmetic Operations for Logic Applications Ieee Transactions On Electron Devices. 64: 2977-2983 |
| Guckert L, Swartzlander EE. (2017) MAD Gates—Memristor Logic Design Using Driver Circuitry Ieee Transactions On Circuits and Systems Ii-Express Briefs. 64: 171-175 |
| Guckert L, Swartzlander EE. (2017) Optimized Memristor-Based Multipliers Ieee Transactions On Circuits and Systems I-Regular Papers. 64: 373-385 |
| Cui X, Dong W, Liu W, et al. (2017) High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes Ieee Transactions On Computers. 66: 1994-2004 |
| Yin P, Wang C, Liu W, et al. (2017) Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications Journal of Signal Processing Systems. 90: 641-654 |
| Cui X, Liu W, Wang S, et al. (2017) Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders Journal of Signal Processing Systems. 90: 409-419 |
| Sohn J, Swartzlander EE. (2016) A Fused Floating-Point Four-Term Dot Product Unit Ieee Transactions On Circuits and Systems I: Regular Papers |