Kedarnath J. Balakrishnan, Ph.D.

Affiliations: 
2004 University of Texas at Austin, Austin, Texas, U.S.A. 
Area:
Electronics and Electrical Engineering
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"Kedarnath Balakrishnan"

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Nur A. Touba grad student 2004 UT Austin
 (New approaches and limits to test data compression for systems-on-chip.)
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Giles G, Wang J, Sehgal A, et al. (2009) Test access mechanism for multiple identical cores Proceedings - International Test Conference
Wang S, Balakrishnan KJ, Wei W. (2008) X-block: An efficient LFSR reseeding-based method to block unknowns for temporal compactors Ieee Transactions On Computers. 57: 978-989
Balakrishnan KJ, Fang L. (2007) RTL test point insertion to reduce delay test volume Proceedings of the Ieee Vlsi Test Symposium. 325-330
Balakrishnan KJ. (2007) Efficient scan-based BIST using multiple LFSRs and dictionary coding Proceedings of the Ieee International Conference On Vlsi Design. 345-350
Balakrishnan KJ, Touba NA. (2007) Relationship between entropy and test data compression Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 386-395
Quming Z, Balakrishnan KJ. (2007) Test cost reduction for SoC using a combined approach to test data compression and test scheduling Proceedings -Design, Automation and Test in Europe, Date. 39-44
Balakrishnan KJ, Wang S, Chakradhar ST. (2006) PIDISC: Pattern independent design independent seed compression technique Proceedings of the Ieee International Conference On Vlsi Design. 2006: 811-817
Balakrishnan KJ, Touba NA. (2006) Improving linear test data compression Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 1227-1237
Wang S, Balakrishnan KJ, Chakradhar ST. (2006) Efficient unknown blocking using LFSR reseeding Proceedings -Design, Automation and Test in Europe, Date. 1
Wang S, Balakrishnan KJ, Chakradhar ST. (2005) XWRC: Externally-loaded weighted random pattern testing for input test data compression Proceedings - International Test Conference. 2005: 571-580
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