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Malgorzata Marek-Sadowska

Affiliations: 
Electrical & Computer Engineering University of California, Santa Barbara, Santa Barbara, CA, United States 
Area:
Electronics and Electrical Engineering
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Children

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Arindam Mukherjee grad student 2002 UC Santa Barbara
Yajun Ran grad student 2005 UC Santa Barbara
Zhiyuan Wang grad student 2005 UC Santa Barbara
Chao-Yang ( Yeh grad student 2005 UC Santa Barbara
Hailin Jiang grad student 2007 UC Santa Barbara
Chung-Kuan Tsai grad student 2007 UC Santa Barbara
Vishal J. Mehta grad student 2008 UC Santa Barbara
Aida Todri grad student 2009 UC Santa Barbara
Yi-Wei Lin grad student 2010 UC Santa Barbara
Nilesh A. Modi grad student 2011 UC Santa Barbara
Jen-Yi Wuu grad student 2011 UC Santa Barbara
Di-an Li grad student 2013 UC Santa Barbara
Xiang Qiu grad student 2013 UC Santa Barbara
Vivek S. Nandakumar grad student 2014 UC Santa Barbara

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Publications

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Yang P, Marek-Sadowska M. (2018) High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators Ieee Transactions On Very Large Scale Integration Systems. 26: 1209-1222
Marek-Sadowska M. (2016) Automated Routing for VLSI: Kuh's Group Contributions Ieee Circuits and Systems Magazine. 16: 35-49
Guan Z, Marek-Sadowska M. (2015) Incorporating Process Variations Into SRAM Electromigration Reliability Assessment Using Atomic Flux Divergence Ieee Transactions On Very Large Scale Integration (Vlsi) Systems
Li DA, Marek-Sadowska M, Nassif SR. (2015) T-VEMA: A Temperature-and Variation-Aware Electromigration Power Grid Analysis Tool Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 2327-2331
Qiu X, Marek-Sadowska M, Maly WP. (2015) Three-dimensional chips can be cool: Thermal study of VeSFET-based 3-D chips Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 869-878
Li DA, Marek-Sadowska M, Nassif SR. (2015) A method for improving power grid resilience to electromigration-caused via failures Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 118-130
Yang PL, Marek-Sadowska M, Maly W. (2015) Performance assessment of VeSFET-based SRAM Proceedings of the 2015 Ieee International Conference On Electron Devices and Solid-State Circuits, Edssc 2015. 79-82
Nandakumar VS, Marek-Sadowska M. (2014) System-level floorplan-aware analysis of integrated CPU-GPUs Proceedings - Design Automation Conference
Qiu X, Marek-Sadowska M, Maly WP. (2014) Characterizing VeSFET-based ICs with CMOS-Oriented EDA infrastructure Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 495-506
Nandakumar VS, Marek-Sadowska M. (2014) On Optimal Kernel Size for Integrated CPU-GPUS - A Case Study Ieee Computer Architecture Letters. 13: 81-84
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