Ashok K. Palaniswamy, Ph.D.
Affiliations: | 2014 | Electrical and Computer Engineering | Southern Illinois University at Carbondale, Carbondale, IL |
Area:
Electronics and Electrical Engineering, Computer EngineeringGoogle:
"Ashok Palaniswamy"Parents
Sign in to add mentorSpyros Tragoudas | grad student | 2014 | SIU Carbondale | |
(Synthesis and testing of threshold logic circuits.) |
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Publications
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Palaniswamy AK, Tragoudas S, Haniotakis T. (2016) ATPG for Delay Defects in Current Mode Threshold Logic Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1903-1913 |
Palaniswamy AK, Tragoudas S. (2014) Improved threshold logic synthesis using implicant-implicit algorithms Acm Journal On Emerging Technologies in Computing Systems. 10 |
Palaniswamy AK, Tragoudas S, Haniotakis T. (2014) ATPG for transition faults of pipelined threshold logic circuits Proceedings - 2014 9th Ieee International Conference On Design and Technology of Integrated Systems in Nanoscale Era, Dtis 2014 |
Palaniswamy AK, Tragoudas S. (2012) An efficient heuristic to identify threshold logic functions Acm Journal On Emerging Technologies in Computing Systems. 8 |
Palaniswamy AK, Tragoudas S. (2012) A scalable threshold logic synthesis method using ZBDDs Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 307-310 |
Palaniswamy AK, Goparaju MK, Tragoudas S. (2010) Scalable identification of threshold logic functions Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 269-273 |
Palaniswamy AK, Goparaju MK, Tragoudas S. (2009) A fault tolerant threshold logic gate design Proceedings of the 13th Wseas International Conference On Circuits - Held as Part of the 13th Wseas Cscc Multiconference. 162-167 |
Goparaju MK, Palaniswamy AK, Tragoudas S. (2008) A fault tolerance aware synthesis methodology for threshold logic gate networks Proceedings - Ieee International Symposium On Defect and Fault Tolerance in Vlsi Systems. 176-183 |