Jongsun Kim, Ph.D.
Affiliations: | 2006 | University of California, Los Angeles, Los Angeles, CA |
Area:
Electronics and Electrical EngineeringGoogle:
"Jongsun Kim"Parents
Sign in to add mentorMau-Chung Frank Chang | grad student | 2006 | UCLA | |
(Design of advanced I/O interconnect circuits and systems in CMOS.) |
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Publications
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Hwang H, Kim J. (2020) A 100 Gb/s Quad-Lane SerDes Receiver with a PI-Based Quarter-Rate All-Digital CDR Electronics. 9: 1113 |
Kim J. (2020) A wide-range all-digital phase inversion DLL for high-speed DRAMs Analog Integrated Circuits and Signal Processing. 102: 39-51 |
Park D, Kim J. (2020) A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-Based All-Digital DLL Circuits Systems and Signal Processing. 39: 1715-1734 |
Hwang H, Kim J. (2019) A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links Ieice Electronics Express. 16: 20190505-20190505 |
Kim J, Shin H. (2018) A Low-power 3.52 Gbps SerDes with a MDLL Frequency Multiplier for High-speed On-chip Networks Journal of Semiconductor Technology and Science. 18: 658-666 |
Kim J, Han S. (2018) A low-power fast-lock DCC with a digital duty-cycle adjuster for LPDDR3 and LPDDR4 DRAMs Ieice Electronics Express. 15: 20180156-20180156 |
Kim J, Bae B. (2018) An anti-harmonic MDLL for phase-aligned on-chip clock multiplication Ieice Electronics Express. 15: 20180042-20180042 |
Kim J. (2018) An anti-boundary switching fine-resolution digital delay-locked loop Analog Integrated Circuits and Signal Processing. 96: 445-454 |
Kim J, Bae B. (2017) A 2-4 GHz fast-locking frequency multiplying delay-locked loop Ieice Electronics Express. 14: 20161056-20161056 |
Yoon J, Heo SW, Kim J. (2017) A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs Ieice Electronics Express. 14: 20161020-20161020 |