Gyung-Su Byun, Ph.D.
Affiliations: | 2010 | University of California, Los Angeles, Los Angeles, CA |
Area:
Electronics and Electrical EngineeringGoogle:
"Gyung-Su Byun"Parents
Sign in to add mentor| Mau-Chung Frank Chang | grad student | 2010 | UCLA | |
| (Multi-band RF-interconnect for future memory interface.) | ||||
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Publications
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| Jalalifar M, Byun G. (2020) An energy-efficient multi-level RF-interconnect for global network-on-chip communication Analog Integrated Circuits and Signal Processing. 102: 131-143 |
| Lin C, Mirzaie N, Alzahmi A, et al. (2019) A Reconfigurable CMOS Power Amplifier Using Adaptive Biasing Technique for Wireless Monitoring Applications Journal of Semiconductor Technology and Science. 19: 511-516 |
| Mirzaie N, Lin C, Alzahmi A, et al. (2019) Reliability-Aware 3-D Clock Distribution Network Using Memristor Ratioed Logic Ieee Transactions On Components, Packaging and Manufacturing Technology. 9: 1847-1854 |
| Mirzaie N, Alzahmi A, Shamsi H, et al. (2018) Three-Dimensional Pipeline ADC Utilizing TSV/ Design Optimization and Memristor Ratioed Logic Ieee Transactions On Very Large Scale Integration Systems. 26: 2619-2627 |
| Mirzaie N, Byun G. (2018) An Optimal Design Methodology for Yield-Improved and Low-Power Pipelined ADC Ieee Transactions On Semiconductor Manufacturing. 31: 130-135 |
| Jalalifar M, Byun G. (2018) A Wide-Range Low-Power PLL-Based PI Multiphase Generator Using an Adaptive Frequency Tracking Technique Ieee Transactions On Circuits and Systems Ii-Express Briefs. 65: 903-907 |
| Mirzaie N, Shamsi H, Byun G. (2017) Automatic Design and Yield Enhancement of Data Converters Journal of Circuits, Systems, and Computers. 26: 1750018 |
| Jalalifar M, Byun G. (2017) An Energy-Efficient Mobile Memory I/O Interface Using Simultaneous Bidirectional Multilevel Dual-Band Signaling Ieee Transactions On Circuits and Systems Ii-Express Briefs. 64: 897-901 |
| Alzahmi A, Mirzaie N, Byun G. (2017) 3-D Power Delivery Network’s Subblocks and Regulator Placement Optimized by Evolutionary Algorithm Ieee Transactions On Components, Packaging and Manufacturing Technology. 7: 2027-2035 |
| Jalalifar M, Byun G. (2017) A low-power low-jitter DLL with a differential closed-loop duty cycle corrector Analog Integrated Circuits and Signal Processing. 93: 149-155 |