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Aida Varzaghani, Ph.D.

Affiliations: 
2007 University of California, Los Angeles, Los Angeles, CA 
Area:
Electronics and Electrical Engineering
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"Aida Varzaghani"
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Chih-Kong K. Yang grad student 2007 UCLA
 (Analog to digital conversion with embedded channel equalization for high-speed serial link receivers.)

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Publications

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Varzaghani A, Yang CKK. (2009) A 4.8 GS/s 5-bit ADC-based receiver with embedded DFE for signal equalization Ieee Journal of Solid-State Circuits. 44: 901-915
Emami-Neyestanak A, Varzaghani A, Bulzacchelli JF, et al. (2007) A 6.0-mW 10.0-Gb/s receiver with switched-capacitor summation DFE Ieee Journal of Solid-State Circuits. 42: 889-896
Varzaghani A, Yang CKK. (2006) A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converter Ieee Journal of Solid-State Circuits. 41: 935-944
Varzaghani A, Yang CKK. (2006) A 600-MS/s 5-bit pipeline A/D converter using digital reference calibration Ieee Journal of Solid-State Circuits. 41: 310-319
Emami-Neyestanak A, Varzaghani A, Bulzacchelli J, et al. (2006) A low-power receiver with switched-capacitor summation DFE Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 192-193
Varzaghani A, Yang CKK. (2005) A 6GS/S, 4-bit receiver analog-to-digital converter with embedded DFE Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 2005: 322-325
Varzaghani A, Yang CKK. (2004) A 600MS/s, 5-bit pipelined Analog-to-Digital Converter for serial-link applications Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 276-279
Varzaghani A, Atarodi M. (2002) A new method to increase the dynamic range of switched Opamp delta-sigma modulators Proceedings - Ieee International Symposium On Circuits and Systems. 2
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