Hemanth Jagannathan, Ph.D.
Affiliations: | 2007 | Stanford University, Palo Alto, CA |
Area:
Electronics and Electrical Engineering, Materials Science EngineeringGoogle:
"Hemanth Jagannathan"Parents
Sign in to add mentor| Yoshio Nishi | grad student | 2007 | Stanford | |
| (Semiconductor nanowires: Synthesis, passivation, and devices.) | ||||
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Publications
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| Siddiqui S, Galatage R, Zhao W, et al. (2020) High quality interfacial layer formation for Si0.75Ge0.25 (100) high-k metal gate stack Microelectronic Engineering. 223: 111219 |
| Martinez E, Nolot E, Barnes J, et al. (2018) Germanium out diffusion in SiGe-based HfO2 gate stacks Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena. 36: 42902 |
| Cooper D, Bernier N, Rouvière JL, et al. (2017) High-precision deformation mapping in finFET transistors with two nanometre spatial resolution by precession electron diffraction. Applied Physics Letters. 110: 223109 |
| Mochizuki S, Loesing R, Wang Y, et al. (2017) Study of phosphorus doped Si:C films formed by in situ doped Si epitaxy and implantation process for n-type metal-oxide-semiconductor devices Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena. 35: 21208 |
| Jamison PC, Tsunoda T, Vo TA, et al. (2015) SiO₂ Free HfO₂ Gate Dielectrics by Physical Vapor Deposition Ieee Transactions On Electron Devices |
| Wang M, Muralidhar R, Stathis JH, et al. (2013) Superior PBTI reliability for SOI FinFET technologies and its physical understanding Ieee Electron Device Letters. 34: 837-839 |
| Manabe K, Watanabe K, Jagannathan H, et al. (2013) Mechanism for leakage reduction by la incorporation in a HfO 2SiO2Si gate stack Ieee Electron Device Letters. 34: 348-350 |
| Hopstaken MJP, Pfeiffer D, Copel M, et al. (2013) Physical characterization of sub-32-nm semiconductor materials and processes using advanced ion beam-based analytical techniques Surface and Interface Analysis. 45: 338-344 |
| Maitra K, Khakifirooz A, Kulkarni P, et al. (2011) Aggressively scaled strained-silicon-on-insulator undoped-body High-κ/Metal-Gate nFinFETs for high-performance logic applications Ieee Electron Device Letters. 32: 713-715 |
| Kim SB, Zhang Y, McVittie JP, et al. (2008) Integrating phase-change memory cell with Ge nanowire diode for crosspoint memory - Experimental demonstration and analysis Ieee Transactions On Electron Devices. 55: 2307-2313 |