Bendik Kleveland, Ph.D.
Affiliations: | 2000 | Stanford University, Palo Alto, CA |
Area:
Electronics and Electrical EngineeringGoogle:
"Bendik Kleveland"Parents
Sign in to add mentor| S Simon Wong | grad student | 2000 | Stanford | |
| (CMOS interconnects beyond 10 GHz.) | ||||
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Publications
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| Vamvakos SD, Gauthier CR, Rao C, et al. (2014) A 2.488-11.2 Gb/s SerDes in 40 nm low-leakage CMOS with multi-protocol compatibility for FPGA applications Analog Integrated Circuits and Signal Processing. 78: 259-273 |
| Vamvakos SD, Gauthier CR, Rao C, et al. (2012) A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications Midwest Symposium On Circuits and Systems. 5-8 |
| Johnson M, Al-Shamma A, Bosch D, et al. (2003) 512-Mb PROM with a three-dimensional array of diode/antifuse memory cells Ieee Journal of Solid-State Circuits. 38: 1920-1928 |
| Wong SS, Yue P, Chang R, et al. (2003) On-chip interconnect inductance - friend or foe Proceedings - International Symposium On Quality Electronic Design, Isqed. 2003: 389-394 |
| Kleveland B, Diaz CH, Vook D, et al. (2002) Correction to "exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design" Ieee Journal of Solid-State Circuits. 37: 255-255 |
| Kleveland B, Qi X, Madden L, et al. (2002) High-frequency characterization of on-chip digital interconnects Ieee Journal of Solid-State Circuits. 37: 716-725 |
| Kleveland B, Diaz CH, Vook D, et al. (2001) Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design Ieee Journal of Solid-State Circuits. 36: 1480-1488 |
| Kleveland B, Maloney TJ, Morgan I, et al. (2000) Distributed ESD protection for high-speed integrated circuits Ieee Electron Device Letters. 21: 390-392 |
| Qi X, Kleveland B, Yu Z, et al. (2000) On-chip inductance modeling of VLSI interconnects Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 172-173 |