Vivekananda M. Vedula, Ph.D.
Affiliations: | 2003 | University of Texas at Austin, Austin, Texas, U.S.A. |
Area:
Computer Science, Electronics and Electrical EngineeringGoogle:
"Vivekananda Vedula"Parents
Sign in to add mentor| Jacob A. Abraham | grad student | 2003 | UT Austin | |
| (HDL slicing for verification and test.) | ||||
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Publications
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| Hari SKS, Konda VVR, Kamakoti V, et al. (2008) Automatic constraint based test generation for behavioral HDL models Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 408-421 |
| Vedula VM, Andersen FL, Abraham JA. (2006) Taming the complexity of STE-based design verification using program slicing Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 137-142 |
| Vedula VM, Townsend WJ, Abraham JA. (2004) Program slicing for ATPG-based property checking Proceedings of the Ieee International Conference On Vlsi Design. 17: 591-596 |
| Saab DG, Abraham JA, Vedula VM. (2003) Formal verification using bounded model checking: SAT versus sequential ATPG engines Proceedings of the Ieee International Conference On Vlsi Design. 2003: 243-248 |
| Vedula VM, Abraham JA, Bhadra J, et al. (2003) A hierarchical test generation approach using program slicing techniques on hardware description languages Journal of Electronic Testing: Theory and Applications (Jetta). 19: 149-160 |
| Vedula VM, Abraham JA, Bhadra J. (2002) Program slicing for hierarchical test generation Proceedings of the Ieee Vlsi Test Symposium. 2002: 237-243 |
| Jayaraman K, Vedula VM, Abraham JA. (2002) Native mode functional self-test generation for Systems-on-Chip Proceedings - International Symposium On Quality Electronic Design, Isqed. 2002: 280-285 |
| Vedula VM, Abraham JA. (2002) FACTOR: A hierarchical methodology for functional test generation and testability analysis Proceedings -Design, Automation and Test in Europe, Date. 730-734 |
| Abraham JA, Vedula VM, Saab DG. (2002) Verifying properties using sequential ATPG Ieee International Test Conference (Tc). 194-202 |
| Vedula VM, Abraham JA. (2000) A novel methodology for hierarchical test generation using functional constraint composition Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 2000: 9-14 |