Brian Cherkauer
Affiliations: | 1995 | Electrical and Computer Engineering | University of Rochester, Rochester, NY |
1995- | Intel Corporation, Santa Clara, CA, United States |
Area:
Thesis: CMOS-Based Architectural and Circuit Design Techniques for Application to High Speed, Low Power MultiplicationGoogle:
"Brian Cherkauer"
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Publications
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Tarn S, Rusu S, Chang J, et al. (2006) A 65nm 95W dual-core multi-threaded Xeon® processor with L3 cache 2006 Ieee Asian Solid-State Circuits Conference, Asscc 2006. 15-18 |
Rusu S, Stinson J, Tam S, et al. (2003) A 1.5-GHz 130-nm Itanium® 2 processor with 6-MB on-die L3 cache Ieee Journal of Solid-State Circuits. 38: 1887-1895 |
Cherkauer BS, Friedman EG. (1997) A hybrid radix-4/radix-8 low power signed multiplier architecture Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 44: 656-659 |
Cherkauer BS, Friedman EG. (1995) A Unified Design Methodology for CMOS Tapered Buffers Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 3: 99-111 |
Cherkauer BS, Friedman EG. (1995) Design of Tapered Buffers with Local Interconnect Capacitance Ieee Journal of Solid-State Circuits. 30: 151-155 |
Cherkauer BS, Friedman EG. (1994) Channel Width Tapering of Serially Connected Mosfet's with Emphasis on Power Dissipation Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 2: 100-114 |