Sherif A. Tawfik
Affiliations: | 2009 | Electrical and Computer Engineering | University of Wisconsin, Madison, Madison, WI |
| 2009- | Intel Corporation, Santa Clara, CA, United States |
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"Sherif Tawfik"Parents
Sign in to add mentor| Volkan Kursun | grad student | 2009 | UW Madison | |
| (Digital circuit methodologies for low power and robust nanoscale integration.) | ||||
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Publications
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| Tawfik SA, Kursun V. (2011) Multi-threshold voltage FinFET sequential circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 151-156 |
| Tawfik SA, Kursun V. (2010) Dual supply voltages and dual clock frequencies for lower clock power and suppressed temperature-gradient-induced clock skew Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 347-355 |
| Tawfik SA, Kursun V. (2009) Robust FinFET memory circuits with P-type data access transistors for higher integration density and reduced leakage power Journal of Low Power Electronics. 5: 497-508 |
| Tawfik SA, Kursun V. (2009) Low power and high speed multi threshold voltage interface circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 638-645 |
| Tawfik SA, Kursun V. (2009) FinFET technology development guidelines for higher performance, lower power, and stronger resilience to parameter variations Midwest Symposium On Circuits and Systems. 431-434 |
| Tawfik SA, Kursun V. (2009) Manufacturable low-power latches for standard tied-double-gate FinFET technologies Midwest Symposium On Circuits and Systems. 471-474 |
| Tawfik SA, Kursun V. (2009) Mutual exploration of FinFET technology and circuit design options for implementing compact brute-force latches 2009 1st Asia Symposium On Quality Electronic Design, Asqed 2009. 1-8 |
| Tawfik SA, Kursun V. (2009) Parameter space exploration for robust and high-performance n-channel and p-channel symmetric double-gate FinFETs 2009 1st Asia Symposium On Quality Electronic Design, Asqed 2009. 246-251 |
| Tawfik SA, Kursun V. (2009) FinFET domino logic with independent gate keepers Microelectronics Journal. 40: 1531-1540 |
| Tawfik SA, Kursun V. (2009) Low-power and robust six-finFET memory cell using selective gate-drain/source overlap engineering Isic-2009 - 12th International Symposium On Integrated Circuits, Proceedings. 244-247 |