Baris Taskin
Affiliations: | 2005 | Electrical and Computer Engineering | University of Pittsburgh, Pittsburgh, PA, United States |
2005- | Electrical and Computer Engineering | Drexel University, Philadelphia, PA, United States |
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"Baris Taskin"Parents
Sign in to add mentorIvan S. Kourtev | grad student | 2005 | University of Pittsburgh | |
(Advanced timing and synchronization methodologies for digital VLSI integrated circuits.) |
Children
Sign in to add traineeVinayak Honkote | grad student | 2010 | Drexel |
Jianchao Lu | grad student | 2011 | Drexel |
Ankit More | grad student | 2013 | Drexel |
Ying Teng | grad student | 2014 | Drexel |
Can Sitik | grad student | 2015 | Drexel |
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Publications
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Pano V, Tekin I, Yilmaz I, et al. (2020) TSV Antennas for Multi-Band Wireless Communication Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 10: 100-113 |
Pano V, Tekin I, Liu Y, et al. (2020) TSV-based antenna for on-chip wireless communication Iet Microwaves Antennas & Propagation. 14: 302-307 |
Liu W, Sitik C, Salman E, et al. (2019) SLECTS: Slew-Driven Clock Tree Synthesis Ieee Transactions On Very Large Scale Integration Systems. 27: 864-874 |
Lerner S, Yilmaz I, Taskin B. (2019) Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors Ieee Transactions On Very Large Scale Integration Systems. 27: 700-710 |
Lerner S, Taskin B. (2019) Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis Ieee Transactions On Very Large Scale Integration Systems. 27: 1-10 |
Filippini L, Taskin B. (2019) The Adiabatically Driven StrongARM Comparator Ieee Transactions On Circuits and Systems Ii-Express Briefs. 66: 1957-1961 |
Kuttappa R, Kose S, Taskin B. (2019) FOPAC : Flexible On-Chip Power and Clock Ieee Transactions On Circuits and Systems I-Regular Papers. 66: 4628-4636 |
Kuttappa R, Balaji A, Pano V, et al. (2019) RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer Ieee Transactions On Circuits and Systems I-Regular Papers. 66: 2685-2698 |
Sangaiah K, Lui M, Jagtap R, et al. (2018) SynchroTrace: Synchronization-Aware Architecture-Agnostic Traces for Lightweight Multicore Simulation of CMP and HPC Workloads Acm Transactions On Architecture and Code Optimization. 15: 2 |
More A, Pano V, Taskin B. (2018) Vertical Arbitration-Free 3-D NoCs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 1853-1866 |