Faquir C. Jain
Affiliations: | Electrical and Computer Engineering | University of Connecticut, Storrs, CT, United States |
Area:
Electronics and Electrical Engineering, Materials Science EngineeringGoogle:
"Faquir Jain"Bio:
https://ieeexplore.ieee.org/author/37318777900
DOI: 10.1063/1.88311 The author wishes to thank Professor MA Melehy for carefully going through the manuscript and making useful suggestions, ...
Parents
Sign in to add mentor| Mahmoud A. Melehy | grad student | 1973 | University of Connecticut | |
| (Low-temperature epitaxially-grown Ge-GaAs and Ge-ZnSe heterojunctions) | ||||
Children
Sign in to add trainee| Fuad H. Al-Amody | grad student | 2011 | University of Connecticut |
| Mukesh Gogna | grad student | 2011 | University of Connecticut |
| Supriya Karmakar | grad student | 2011 | University of Connecticut |
| Robert A. Croce | grad student | 2012 | University of Connecticut |
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Publications
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| Gudlavalleti RH, Saman B, Mays R, et al. (2019) Modeling of Multi-State Si and Ge Cladded Quantum Dot Gate FETs Using Verilog and ABM Simulations International Journal of High Speed Electronics and Systems. 28: 1940026 |
| Salama H, Saman B, Gudlavalleti RH, et al. (2019) Simulation of Stacked Quantum Dot Channels SWS-FET Using Multi-FET ABM Modeling International Journal of High Speed Electronics and Systems. 28: 1940025 |
| Jain F, Saman B, Gudlavalleti RH, et al. (2019) Multi-Bit SRAMs, Registers, and Logic Using Quantum Well Channel SWS-FETs for Low-Power, High-Speed Computing International Journal of High Speed Electronics and Systems. 28: 1940024 |
| Jain F, Gudlavalleti RH, Mays R, et al. (2019) Integration of Quantum Dot Gate (QDG) in SWS-FETs for Multi-Bit Logic and QD-NVRAMs for Distributed In-Memory Computing International Journal of High Speed Electronics and Systems. 28: 1940018 |
| Karmakar S, Gogna M, Jain F. (2019) Fabrication of QDNVM-based comparator Micro & Nano Letters. 14: 947-951 |
| Karmakar S, Chandy JA, Jain FC. (2019) Eight-bit ADC using non-volatile flash memory Iet Circuits, Devices & Systems. 13: 98-102 |
| Salama H, Saman B, Heller E, et al. (2018) Twin Drain Quantum Well/Quantum Dot Channel Spatial Wave-Function Switched (SWS) FETs for Multi-Valued Logic and Compact DRAMs International Journal of High Speed Electronics and Systems. 27: 1840024 |
| Jain F, Saman B, Gudlavalleti RH, et al. (2018) Multi-State 2-Bit CMOS Logic Using n- and p- Quantum Well Channel Spatial Wavefunction Switched (SWS) FETs International Journal of High Speed Electronics and Systems. 27: 1840020 |
| Saman B, Heller E, Jain FC. (2018) A Novel One SWS-FET Transistor for AND/OR Logic Gate International Journal of High Speed Electronics and Systems. 27: 1840019 |
| Lingalugari M, Heller E, Parthasarathy B, et al. (2018) Quantum Dot Floating Gate Nonvolatile Random Access Memory Using Ge Quantum Dot Channel for Faster Erasing International Journal of High Speed Electronics and Systems. 27: 1840006 |