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Uma Chilakapati, Ph.D.

Affiliations: 
2000 Washington State University, Pullman, WA, United States 
Area:
Electronics and Electrical Engineering
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Terri S. Fiez grad student 2000 WSU
 (Circuit techniques and performance optimization for high-speed CMOS analog signal processing.)

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Publications

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Chilakapati U, Fiez TS, Eshraghi A. (2002) A CMOS transconductor with 80-dB SFDR up to 10 MHz Ieee Journal of Solid-State Circuits. 37: 365-370
Chilakapati U, Fiez T, Eshraghi A. (2001) A 3.3V transconductor in 0.35μm CMOS with 80dB SFDR up to 10MHz Proceedings of the Custom Integrated Circuits Conference. 459-462
Chilakapati U, Fiez TS. (1999) Effect of switch resistance on the SC integrator settling time Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 46: 810-816
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