Andrzej Strojwas
Affiliations: | Carnegie Mellon University, Pittsburgh, PA |
Area:
Electronics and Electrical EngineeringWebsite:
https://www.ece.cmu.edu/directory/bios/strojwas-andrzej.htmlGoogle:
"Andrzej Strojwas"Bio:
https://www.proquest.com/openview/3315348baf9e06d689749b2db6dc7e1e/1
Parents
Sign in to add mentor| Stephen W. Director | grad student | 1982 | Carnegie Mellon (Computer Science Tree) | |
| (Pattern recognition based methods for IC failure analysis) | ||||
Children
Sign in to add trainee| Michele Quarantelli | grad student | 2003 | Carnegie Mellon |
| Zhengrong Zhu | grad student | 2004 | Carnegie Mellon |
| Yaping Zhan | grad student | 2005 | Carnegie Mellon |
| Michal J. Palusinski | grad student | 2007 | Carnegie Mellon |
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Publications
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| Vaidyanathan K, Zhu Q, Liebmann L, et al. (2015) Exploiting sub-20-nm complementary metal-oxide semiconductor technology challenges to design affordable systems-on-chip Journal of Micro/ Nanolithography, Mems, and Moems. 14 |
| Vaidyanathan K, Liu R, Liebmann L, et al. (2014) Design implications of extremely restricted patterning Journal of Micro/ Nanolithography, Mems, and Moems. 13 |
| Vaidyanathan K, Liu R, Liebmann L, et al. (2013) Rethinking ASIC design with next generation lithography and process integration Proceedings of Spie - the International Society For Optical Engineering. 8684 |
| Vaidyanathan K, Ng SH, Morris D, et al. (2012) Design and manufacturability tradeoffs in unidirectional & bidirectional standard cell layouts in 14 nm node Proceedings of Spie - the International Society For Optical Engineering. 8327 |
| Rovner VV, Jhaveri T, Morris D, et al. (2011) Performance and manufacturability trade-offs of pattern minimization for sub-22nm technology nodes Proceedings of Spie - the International Society For Optical Engineering. 7974 |
| Jhaveri T, Arslan U, Rovner V, et al. (2010) Application of the cost-per-good-die metric for process design co-optimization Proceedings of Spie - the International Society For Optical Engineering. 7641 |
| Miyamoto K, Strojwas A, Hosomi E, et al. (2010) Novel circuit design and process technology for leading-edge products Digest of Technical Papers - Symposium On Vlsi Technology. 141-142 |
| Jhaveri T, Rovner V, Liebmann L, et al. (2010) Co-optimization of circuits, layout and lithography for predictive technology scaling beyond gratings Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 509-527 |
| Jhaveri T, Stobert I, Liebmann L, et al. (2009) OPC simplification and mask cost reduction using regular design fabrics Proceedings of Spie - the International Society For Optical Engineering. 7274 |
| Jhaveri T, Strojwas A, Pileggi L, et al. (2008) Enabling technology scaling with "in production" lithography processes Proceedings of Spie - the International Society For Optical Engineering. 6924 |