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Daniel F. Baldwin

Affiliations: 
Georgia Institute of Technology, Atlanta, GA 
Area:
Mechanical Engineering, Materials Science Engineering, Packaging Engineering
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"Daniel Baldwin"
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Parents

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Children

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Ruijun Chen grad student 2003 Georgia Tech
Chunho Kim grad student 2003 Georgia Tech
Jennifer V. Muncy grad student 2004 Georgia Tech
Sung C. Joo grad student 2009 Georgia Tech

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Publications

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Bhattacharya S, Xie F, Baldwin DF, et al. (2016) Process and Evaluation of High Reliability Reworkable Edge Bond Adhesives for Large Area BGA Applications Additional Conferences (Device Packaging, Hitec, Hiten, and Cicmt). 2016: 002018-002053
Fennell B, Lee S, Baldwin DF. (2016) Rotational solder self-alignment mechanics modeling for a flip chip in the presence of a viscous fluid Microelectronics Reliability. 65: 217-224
Bhattacharya SK, Lewis B, Wu H, et al. (2015) Reliability assessment of thermally compression bonded copper pillar on organic and ceramic substrates Proceedings - Electronic Components and Technology Conference. 2015: 2077-2082
Lee S, Baldwin DF. (2013) Heterogeneous Void Nucleation Study in Flip Chip Assembly Process Using No-Flow Underfill Journal of Electronic Packaging. 136
Lewis BJ, Baldwin DF, Houston PN, et al. (2013) Single chip plated Ni/Pd over ALCAP bond pads for flip chip applications and prototyping Proceedings - Electronic Components and Technology Conference. 1564-1568
Lewis BJ, Baldwin DF, Houston PN, et al. (2012) Processing, Bumping and Assembly of Single Chip Plated Ni/Pd over ALCAP Bond Pads for Flip Chip Applications and Prototyping Additional Conferences (Device Packaging, Hitec, Hiten, and Cicmt). 2012: 001841-001869
Lee S, Yim MJ, Baldwin D. (2012) Effect of nano-particles on heterogeneous void nucleation in no-flow underfill materials Ieee Transactions On Components, Packaging and Manufacturing Technology. 2: 1059-1063
Lewis BJ, Baldwin DF, Houston PN, et al. (2011) Processing and Reliability Assessment of Silicon Based, Integrated Ultra High Density Substrates Additional Conferences (Device Packaging, Hitec, Hiten, and Cicmt). 2011: 002272-002313
Li Z, Lee S, Evans JL, et al. (2011) Comprehensive study of lead-free reflow process for a 3-D flip chip on silicon package Ieee Transactions On Components, Packaging and Manufacturing Technology. 1: 1856-1863
Lee S, Baldwin DF. (2010) High Yield, Near Void-Free Assembly Process of a Flip Chip in Package Using No-Flow Underfill International Symposium On Microelectronics. 2010: 000798-000805
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