Keunwoo Kim, Ph.D.
Affiliations: | 2001 | University of Florida, Gainesville, Gainesville, FL, United States |
Area:
Electronics and Electrical EngineeringGoogle:
"Keunwoo Kim"Parents
Sign in to add mentor| Jerry G. Fossum | grad student | 2001 | UF Gainesville | |
| (Design and analysis of double -gate CMOS for low-voltage integrated circuit applications, including physical modeling of silicon -on -insulator MOSFETs.) | ||||
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Publications
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| Kim KW, Oh H, Bae J, et al. (2017) Electrostatic-Force-Assisted Dispensing Printing of Electrochromic Gels for Low-Voltage Displays. Acs Applied Materials & Interfaces |
| Joshi RV, Kim K, Kanj R, et al. (2015) Super fast physics-based methodology for accurate memory yield prediction Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 534-543 |
| Kim K, Kanj R, Joshi RV. (2014) Impact of FinFET technology for power gating in nano-scale design Proceedings - International Symposium On Quality Electronic Design, Isqed. 543-547 |
| Liao Y, Chiang M, Kim K, et al. (2012) Assessment of structure variation in silicon nanowire FETs and impact on SRAM Microelectronics Journal. 43: 300-304 |
| Kim K, Kuang JB, Gebara FH, et al. (2009) TCAD/physics-based analysis of high-density dual-BOX FD/SOI SRAM cell with improved stability Ieee Transactions On Electron Devices. 56: 3033-3040 |
| Wei L, Deng J, Chang LW, et al. (2009) Selective device structure scaling and parasitics engineering: A way to extend the technology roadmap Ieee Transactions On Electron Devices. 56: 312-320 |
| Kuang JB, Kim K, Chuang C, et al. (2008) Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 1657-1665 |
| Bansal A, Kim J, Kim K, et al. (2008) Optimal Dual-$V_{T}$ Design in Sub-100-nm PD/SOI and Double-Gate Technologies Ieee Transactions On Electron Devices. 55: 1161-1169 |
| Mukhopadhyay S, Kim K, Chuang CT. (2008) Device design and optimization methodology for leakage and variability reduction in sub-45-nm FD/SOI SRAM Ieee Transactions On Electron Devices. 55: 152-162 |
| Mukhopadhyay S, Kim K, Jenkins KA, et al. (2008) An on-chip test structure and digital measurement method for statistical characterization of local random variability in a process Ieee Journal of Solid-State Circuits. 43: 1951-1963 |