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| Lin Y, Jiang Z, Gu J, et al. (2020) DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1 |
| Lin Y, Li W, Gu J, et al. (2020) ABCDPlace: Accelerated Batch-based Concurrent Detailed Placement on Multi-threaded CPUs and GPUs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1 |
| Li W, Pan DZ. (2019) A New Paradigm for FPGA Placement Without Explicit Packing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 2113-2126 |
| Li M, Yu B, Lin Y, et al. (2019) A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 1585-1598 |
| Li W, Lin Y, Li M, et al. (2018) UTPlaceF 2.0 Acm Transactions On Design Automation of Electronic Systems. 23: 1-23 |
| Li W, Dhar S, Pan DZ. (2018) UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 869-882 |