Year |
Citation |
Score |
2020 |
Bae B, Kim J, Han KJ. Numerical Verification of Dielectric Contactor as Auxiliary Loads for Measuring the Multi-Port Network Parameter of Vertical Interconnection Array Ieee Access. 8: 117997-118004. DOI: 10.1109/Access.2020.3003231 |
0.303 |
|
2019 |
Cho M, Noguchi S, Bang J, Kim J, Bong U, Lee JT, An SB, Bhattarai KR, Kim K, Kim K, Im C, Han KJ, Hahn S. Combined Circuit Model to Simulate Post-Quench Behaviors of No-Insulation HTS Coil Ieee Transactions On Applied Superconductivity. 29: 1-5. DOI: 10.1109/Tasc.2019.2899501 |
0.308 |
|
2019 |
Yea M, Park J, Lee S, Choi J, Han KJ. Optimization of Lead Insulations for HVDC Converter Transformers Journal of Electrical Engineering & Technology. 14: 2057-2063. DOI: 10.1007/S42835-019-00195-W |
0.304 |
|
2018 |
Yea M, Han KJ, Park J, Lee S, Choi J. Design optimization for the insulation of HVDC converter transformers under composite electric stresses Ieee Transactions On Dielectrics and Electrical Insulation. 25: 253-262. DOI: 10.1109/Tdei.2018.006629 |
0.334 |
|
2018 |
Han KJ, Ahn S. Foreword: Special Section on Recent Progress in the Electrical Design of Advanced Package and Systems (Part 2) Ieee Transactions On Components, Packaging and Manufacturing Technology. 8: 3-4. DOI: 10.1109/Tcpmt.2017.2787938 |
0.346 |
|
2016 |
Park HP, Ryu Y, Han KJ, Jung JH. Design considerations of resonant network and transformer magnetics for high frequency LLC resonant converter Journal of Electrical Engineering and Technology. 11: 383-392. DOI: 10.5370/Jeet.2016.11.2.383 |
0.333 |
|
2016 |
Kim S, Kang S, Han KJ, Kim Y. Novel adaptive power-gating strategy and tapered TSV structure in multilayer 3D IC Acm Transactions On Design Automation of Electronic Systems. 21. DOI: 10.1145/2894752 |
0.328 |
|
2016 |
Jeong J, Kim J, Kang N, Han KJ. High-Frequency Testing of Vertical Interconnection Array Using Indirect Contact Probing Method With an Improved Calibration Ieee Transactions On Components, Packaging and Manufacturing Technology. 6: 1638-1647. DOI: 10.1109/Tcpmt.2016.2613823 |
0.361 |
|
2015 |
Ryu Y, Park BR, Han KJ. Estimation of high-frequency parameters of AC machine from transmission line model Ieee Transactions On Magnetics. 51. DOI: 10.1109/Tmag.2014.2355718 |
0.361 |
|
2015 |
Xie B, Swaminathan M, Han KJ. FDFD Nonconformal Domain Decomposition Method for the Electromagnetic Modeling of Interconnections in Silicon Interposer Ieee Transactions On Electromagnetic Compatibility. DOI: 10.1109/Temc.2015.2405014 |
0.486 |
|
2015 |
Jeong J, Kim J, Kang N, Han KJ. Indirect Contact Probing Method for Characterizing Vertical Interconnections in Electronic Packaging Ieee Microwave and Wireless Components Letters. 25: 70-72. DOI: 10.1109/Lmwc.2014.2369951 |
0.302 |
|
2014 |
Han KJ, Lim Y, Kim Y. A performance analysis for interconnections of 3D ICs with frequency-dependent TSV model in S-parameter Journal of Semiconductor Technology and Science. 14: 649-657. DOI: 10.5573/Jsts.2014.14.5.649 |
0.389 |
|
2014 |
Han KJ, Swaminathan M, Jeong J. Modeling of Through-Silicon Via (TSV) Interposer Considering Depletion Capacitance and Substrate Layer Thickness Effects Ieee Transactions On Components, Packaging and Manufacturing Technology. DOI: 10.1109/Tcpmt.2014.2372771 |
0.545 |
|
2013 |
Orlandi A, Swaminathan M, Han KJ. Book review: Design and modeling for 3D ICs and interposers Ieee Electromagnetic Compatibility Magazine. 2: 48-49. DOI: 10.1109/Memc.2013.6714696 |
0.495 |
|
2011 |
Bandyopadhyay T, Han KJ, Chung D, Chatterjee R, Swaminathan M, Tummala R. Rigorous Electrical Modeling of Through Silicon Vias (TSVs) With MOS Capacitance Effects Ieee Transactions On Components, Packaging and Manufacturing Technology. 1: 893-903. DOI: 10.1109/Tcpmt.2011.2120607 |
0.62 |
|
2010 |
Han KJ, Swaminathan M, Bandyopadhyay T. Electromagnetic modeling of through-silicon via (TSV) interconnections using cylindrical modal basis functions Ieee Transactions On Advanced Packaging. 33: 804-817. DOI: 10.1109/Tadvp.2010.2050769 |
0.621 |
|
2009 |
Han KJ, Swaminathan M. Inductance and resistance calculations in three-dimensional packaging using cylindrical conduction-mode basis functions Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 846-859. DOI: 10.1109/Tcad.2009.2016642 |
0.544 |
|
2008 |
Han KJ, Takeuchi H, Swaminathan M. Eye-pattern design for high-peed differential links using extended passive equalization Ieee Transactions On Advanced Packaging. 31: 246-257. DOI: 10.1109/Tadvp.2008.915849 |
0.476 |
|
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