Charles C. Weems

Affiliations: 
University of Massachusetts, Amherst, Amherst, MA 
Area:
Computer Science, Statistics
Google:
"Charles Weems"
Bio:

https://books.google.com/books?id=PH1UAAAAYAAJ

Parents

Sign in to add mentor
Caxton C. Foster grad student 1984 U Mass Amherst (Computer Science Tree)
 (Image Processing on a Content Addressable Array Parallel Processor)
BETA: Related publications

Publications

You can help our author matching system! If you notice any publications incorrectly attributed to this author, please sign in and mark matches as correct or incorrect.

Emmart N, Chen Y, Weems CC. (2015) Computing the Smallest Eigenvalue of Large Ill-Conditioned Hankel Matrices Communications in Computational Physics. 18: 104-124
Lee DH, Yoon SK, Kim JG, et al. (2015) A new memory-disk integrated system with HW optimizer Acm Transactions On Architecture and Code Optimization. 12
Weems CC, Kerbyson DJ, Rajamony R. (2014) Guest editors' note: Special issue on large-scale parallel processing Parallel Processing Letters. 24
Wang W, Huang X, Emmart N, et al. (2014) VLSI Design of a Large-Number Multiplier for Fully Homomorphic Encryption Ieee Transactions On Very Large Scale Integration Systems. 22: 1879-1887
Emmart N, Weems CC. (2013) Search-Based Automatic Code Generation For Multiprecision Modular Exponentiation On Multiple Generations Of Gpu Parallel Processing Letters. 23: 1340009
Choi IS, Jang SI, Oh CH, et al. (2013) A dynamic adaptive converter and management for PRAM-based main memory Microprocessors and Microsystems. 37: 554-561
Park SH, Park JW, Kim SD, et al. (2012) A pattern adaptive NAND flash memory storage structure Ieee Transactions On Computers. 61: 134-138
Emmart N, Weems CC. (2011) High precision integer multiplication with a GPU using Strassen's algorithm with multiple FFT sizes Parallel Processing Letters. 21: 359-375
Weems CC, Kerbyson DJ, Rajamony R. (2011) Guest Editor's note: Large-scale parallel processing Parallel Processing Letters. 21: 275-277
Park JW, Park SH, Weems CC, et al. (2011) A hybrid flash translation layer design for SLC-MLC flash memory based multibank solid state disk Microprocessors and Microsystems. 35: 48-59
See more...