Shahin Golshan, Ph.D.
Affiliations: | 2011 | Information and Computer Science - Ph.D. | University of California, Irvine, Irvine, CA |
Area:
Computer Science, Computer EngineeringGoogle:
"Shahin Golshan"Parents
Sign in to add mentorEli Bozorgzadeh | grad student | 2011 | UC Irvine | |
(Reliability-Aware CAD Tools for SRAM-Based FPGAs.) |
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Publications
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Golshan S, Khajeh A, Homayoun H, et al. (2011) Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations Embedded Systems Week 2011, Esweek 2011 - Proceedings of the 9th Ieee/Acm/Ifip International Conference On Hardware/Software Codesign and System Synthesis, Codes+Isss'11. 257-266 |
Homayoun H, Sasan A, Veidenbaum AV, et al. (2011) MZZ-HVS: Multiple sleep modes zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 2303-2316 |
Golshan S, Kooti H, Bozorgzadeh E. (2011) SEU-aware high-level data path synthesis and layout generation on SRAM-based FPGAs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 829-840 |
Golshan S, Singhal L, Bozorgzadeh E. (2011) Process variation aware system-level load assignment for total energy minimization using stochastic ordering Proceedings of the 12th International Symposium On Quality Electronic Design, Isqed 2011. 566-571 |
Homayoun H, Golshan S, Bozorgzadeh E, et al. (2011) On leakage power optimization in clock tree networks for ASICs and general-purpose processors Sustainable Computing: Informatics and Systems. 1: 75-87 |
Homayoun H, Golshan S, Bozorgzadeh E, et al. (2010) Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks Proceedings of the 11th International Symposium On Quality Electronic Design, Isqed 2010. 499-507 |
Golshan S, Bozorgzadeh E. (2007) Single-Event-Upset (SEU) awareness in FPGA routing Proceedings - Design Automation Conference. 330-333 |