Azad Naeemi, Ph.D.
Affiliations: | 2003 | Georgia Institute of Technology, Atlanta, GA |
Area:
Microelectronics/MicrosystemsGoogle:
"Azad Naeemi"Mean distance: 20.07
Parents
Sign in to add mentor| James D. Meindl | grad student | 2003 | Georgia Tech | |
| (Analysis and optimization for global interconnects for gigascale integration (GSI).) | ||||
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Publications
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| Liao Y, Pan C, Naeemi A. (2020) Benchmarking and Optimization of Spintronic Memory Arrays Ieee Journal On Exploratory Solid-State Computational Devices and Circuits. 6: 9-17 |
| Noor SL, Dens K, Reynaert P, et al. (2020) Modeling and Optimization of Plasmonic Detectors for Beyond-CMOS Plasmonic Majority Logic Gates Journal of Lightwave Technology. 38: 5092-5099 |
| Li X, Lin S, Dc M, et al. (2020) Materials Requirements of High-Speed and Low-Power Spin-Orbit-Torque Magnetic Random-Access Memory Ieee Journal of the Electron Devices Society. 8: 674-680 |
| Lou Q, Pan C, McGuinness J, et al. (2019) A Mixed Signal Architecture for Convolutional Neural Networks Acm Journal On Emerging Technologies in Computing Systems. 15: 1-26 |
| Naeemi A. (2019) Special Topic on Ferroelectric Transistors for Advanced Logic, Analog, and Memory Applications Ieee Journal On Exploratory Solid-State Computational Devices and Circuits. 5: ii-iii |
| Pan C, Lou Q, Niemier M, et al. (2019) Energy-Efficient Convolutional Neural Network Based on Cellular Neural Network Using Beyond-CMOS Technologies Ieee Journal On Exploratory Solid-State Computational Devices and Circuits. 5: 85-93 |
| Pan C, Naeemi A. (2018) Transient Performance Analysis and Optimization of Crossbar Memory Arrays Using NbO2-Based Threshold Switching Selectors Ieee Transactions On Electron Devices. 65: 3214-3220 |
| Hsu C, Pan C, Naeemi A. (2018) Performance Analysis and Enhancement of Negative Capacitance Logic Devices Based on Internally Resistive Ferroelectrics Ieee Electron Device Letters. 39: 765-768 |
| Pan C, Naeemi A. (2018) Complementary Logic Implementation for Antiferromagnet Field-Effect Transistors Ieee Journal On Exploratory Solid-State Computational Devices and Circuits. 4: 69-75 |
| Dutta S, Zografos O, Gurunarayanan S, et al. (2017) Proposal for nanoscale cascaded plasmonic majority gates for non-Boolean computation. Scientific Reports. 7: 17866 |