☰

Changhoon Choi, Ph.D. - Publications

Affiliations: 
2002 Stanford University, Palo Alto, CA 
Tree Info Similar researchers PubMed Report error

16 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2004 Choi C, Chun J, Dutton RW. Electrothermal characteristics of strained-Si MOSFETs in high-current operation Ieee Transactions On Electron Devices. 51: 1928-1931. DOI: 10.1109/Ted.2004.836542  0.587
2003 Choi C, Yu Z, Dutton RW. Resonant gate tunneling current in double-gate SOI: a simulation study Ieee Transactions On Electron Devices. 50: 2579-2581. DOI: 10.1109/Ted.2003.920126  0.465
2003 Choi C, Yu Z, Dutton RW. Impact of poly-gate depletion on MOS RF linearity Ieee Electron Device Letters. 24: 330-332. DOI: 10.1109/Led.2003.812549  0.373
2002 Choi CH, Chidambaram PR, Khamankar R, Machala CF, Yu Z, Dutton RW. Dopant profile and gate geometric effects on polysilicon gate depletion in scaled MOS Ieee Transactions On Electron Devices. 49: 1227-1231. DOI: 10.1109/Ted.2002.1013280  0.475
2002 Kwong MY, Choi C, Kasnavi R, Griffin P, Dutton RW. Series resistance calculation for source/drain extension regions using 2-D device simulation Ieee Transactions On Electron Devices. 49: 1219-1226. DOI: 10.1109/Ted.2002.1013279  0.415
2002 Choi CH, Chidambaram PR, Khamankar R, Machala CF, Yu Z, Dutton RW. Gate length dependent polysilicon depletion effects Ieee Electron Device Letters. 23: 224-226. DOI: 10.1109/55.992846  0.433
2001 Goo J, Choi C, Abramo A, Ahn J, Yu Z, Lee TH, Dutton RW. Physical origin of the excess thermal noise in short channel MOSFETs Ieee Electron Device Letters. 22: 101-103. DOI: 10.1109/55.902845  0.522
2001 Choi C, Nam K, Yu Z, Dutton RW. Impact of gate direct tunneling current on circuit performance: a simulation study Ieee Transactions On Electron Devices. 48: 2823-2829. DOI: 10.1109/16.974710  0.5
2000 Goo J, Choi C, Danneville F, Morifuji E, Momose HS, Yu Z, Iwai H, Lee TH, Dutton RW. An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs Ieee Transactions On Electron Devices. 47: 2410-2419. DOI: 10.1109/16.887030  0.543
2000 Choi CH, Wu Y, Goo JS, Yu Z, Dutton RW. Capacitance reconstruction from measured C-V in high leakage, nitride/oxide MOS Ieee Transactions On Electron Devices. 47: 1843-1850. DOI: 10.1109/16.870559  0.58
2000 Choi CH, Goo JS, Yu Z, Dutton RW. Shallow source/drain extension effects on external resistance in sub-0.1 μm MOSFET's Ieee Transactions On Electron Devices. 47: 655-658. DOI: 10.1109/16.824746  0.579
2000 Choi C, Yu Z, Dutton RW. Modeling of MOS scaling with emphasis on gate tunneling and source/drain resistance Superlattices and Microstructures. 27: 191-206. DOI: 10.1006/Spmi.1999.0799  0.45
1999 Choi C, Goo J, Oh T, Yu Z, Dutton RW, Bayoumi A, Cao M, Voorde PV, Vook D, Diaz CH. MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm) Ieee Electron Device Letters. 20: 292-294. DOI: 10.1109/55.767102  0.62
1997 Park Y, Kang T, Choi C, Kong J, Lee S. Improving the ESD performance of input protection circuits in retrograde well and STI structures Microelectronics Reliability. 37: 1461-1464. DOI: 10.1016/S0026-2714(97)00087-5  0.36
1996 Choi C, Park Y, Lee S, Kim K. Novel ESD protection transistor including SiGe buried layer to reduce local temperature overheating Ieee Transactions On Electron Devices. 43: 479-489. DOI: 10.1109/16.485664  0.382
1995 Sim Jh, Choi CH, Kim K. Elimination of Parasitic Bipolar-Induced Breakdown Effects in Ultra-Thin SOI MOSFET's Using Narrow-Bandgap-Source (NBS) Structure Ieee Transactions On Electron Devices. 42: 1495-1502. DOI: 10.1109/16.398664  0.443
Show low-probability matches.