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Jishen Zhao, Ph.D. - Publications

Affiliations: 
2014 Computer Science and Engineering Pennsylvania State University, State College, PA, United States 
Area:
Computer Engineering
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11 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Yin S, Tang S, Lin X, Ouyang P, Tu F, Liu L, Zhao J, Xu C, Li S, Xie Y, Wei S. Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory Ieee Transactions On Parallel and Distributed Systems. 30: 146-160. DOI: 10.1109/Tpds.2018.2858230  0.665
2019 Dai G, Huang T, Chi Y, Zhao J, Sun G, Liu Y, Wang Y, Xie Y, Yang H. GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 640-653. DOI: 10.1109/Tcad.2018.2821565  0.593
2019 Xie Y, Zhao J. Emerging Memory Technologies Ieee Micro. 39: 6-7. DOI: 10.1109/Mm.2019.2892165  0.598
2018 Sun G, Zhao J, Poremba M, Xu C, Xie Y. Memory that never forgets: emerging nonvolatile memory and the implication for architecture design National Science Review. 5: 577-592. DOI: 10.1093/Nsr/Nwx082  0.689
2017 Zhao J, Zou Q, Xie Y. Overview of 3-D Architecture Design Opportunities and Techniques Ieee Design & Test of Computers. 34: 60-68. DOI: 10.1109/Mdat.2015.2463282  0.485
2016 Zhan J, Ouyang J, Ge F, Zhao J, Xie Y. Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2016.2536747  0.605
2016 Zhao J, Xu C, Zhang T, Xie Y. BACH: A Bandwidth-Aware Hybrid Cache Hierarchy Design with Nonvolatile Memories Journal of Computer Science and Technology. 31: 20-35. DOI: 10.1007/S11390-016-1609-7  0.696
2015 Zhao J, Xu C, Chi P, Xie Y. Memory and storage system design with nonvolatile memory technologies Ipsj Transactions On System Lsi Design Methodology. 8: 2-11. DOI: 10.2197/Ipsjtsldm.8.2  0.68
2015 Zhao J, Li S, Chang J, Byrne JL, Ramirez LL, Lim K, Xie Y, Faraboschi P. Buri: Scaling Big-Memory Computing with Hardware-Based Memory Expansion Acm Transactions On Architecture and Code Optimization. 12: 31. DOI: 10.1145/2808233  0.642
2013 Zhao J, Sun G, Loh GH, Xie Y. Optimizing gpu energy efficiency with 3d die-stacking graphics memory and reconfigurable memory interface Transactions On Architecture and Code Optimization. 10. DOI: 10.1145/2541228.2541231  0.692
2010 Dong X, Zhao J, Xie Y. Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1959-1972. DOI: 10.1109/Tcad.2010.2062811  0.548
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